1 / 27

REXIS OBF Telecon

REXIS OBF Telecon. 2012-01-17 Kevin Ryu, Yvette Grinbush, Deborah Landers, Peter O’Brien, Chris Ward, Keith Warner . Project Goals. Provide the following CCID41s with MBE BI Process and OBF REXIS: Flight program 4x CCID41 Engineering grade units: Mar-2013

moira
Download Presentation

REXIS OBF Telecon

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. REXIS OBFTelecon 2012-01-17 Kevin Ryu, Yvette Grinbush, Deborah Landers, Peter O’Brien, Chris Ward, Keith Warner

  2. Project Goals • Provide the following CCID41s with MBE BI Process and OBF • REXIS: Flight program • 4x CCID41 Engineering grade units: Mar-2013 • 4x CCID41 First flight grade units: Jan-2014 • 4x CCID41 Final flight grade units: Jan-2014 • Directly-Deposited OBF: Process development • Done by 2 year from 2012-7 • 2x CCID41 with no OBF • 2x CCID41 with thick OBF – 220 nm • 2x CCID41 with thin OBF • 2x CCID41 with medium OBF • 2x CCID41 with TBD OBF • Do one coating at a time Required number of CCID41s

  3. Inventory of CCID41s • Diced chips: Cannot be processed in MEL • 41lot1 • FI: 65 chips • BI with Lesser process: 11 chips – 8 functional (including four EM grade devices), 3 non-functional • 53lot1 • BI with MBE: 14 chips – 3 possible flight quality, 1 engineering grade, and 7 functional, 3 non-functional • Wafer format: Can be processed for BI process • 53lot1 • 12 wafers: 48 chips

  4. Key Accomplishments • Chip-level D-D OBF processing • OBF deposited on a functional device from 41lot1 (Lesser Device) • Evaluated two new methods to pattern OBF on non-functional 41lot1 chips • Chose one method to pattern OBF on a functional 41lot1 chip • Optical inspection looks promising • Device to be tested • Testing • Back-illuminated chips from 41lot1 and 53lot1 characterized • 3 flight-grade chip identified: excellent dark current and CTI • REXIS electronics bias condition tested to be functional • Analysis on FI-data done  corner glow not likely a problem • Back-illumination processing • 4 months of processing remaining • Rim-thinned MBE process demonstrated to be good • New gasket for rim-thinning ordered to solve leakage issues

  5. Plans Going Forward • Characterize 41lot1 devices • Characterize 53lot1 devices • Chip-level D-D OBF process on working 41lot1 devices • Re-characterize 41lot1 devices • Chip-level D-D OBF process on working 53lot1 devices • Characterize 53lot1 devices • Deliver working CCID41s with D-D OBF to MKI for testing – Feb. 13 • Process rim-thinned monitor wafers through BI as a pathfinder • Process 5 wafers (4+1 non-functional wafer) in 53lot1 through BI

  6. Questions • Discuss specifications for dark current, CTI, and cosmetics (effective area) • Verify delivery of parts to MITLL • On 1/21/13 • 12 ceramic, 12 aluminum for EM • 1 box for live chips, 1 box for dead chips (packs 4 chips in a box) Arthur (MITLL) to test resistivity to verify that ESD foam is working • Supporting documents Bonding diagrams • Shorting bars • On 2/8/13 • 8 flexprints (only 4 populated)

  7. REXIS/OBF CCID41 Testing Status 2013-1-15 Chris Ward, Kevin Ryu

  8. Recent Testing Overview

  9. BI-41-1-(5-9, 8-1, 8-9) Lesser Devices+10C, Cosmetics • Lesser devices exhibit ~ 8x higher DC than our best MBE devices (roughly 300pA/cm) at +10C • Defects cool out • Blotches that appear as 5000-10000DN at +10C are reduced to ~200DN at -40C Lesser Part at +10C Lesser Part at -40C

  10. MBE BI-53_41-1 Wafer 2 and Wafer 13Streaks and Growth Rings 53_41-1-13-4 53_41-1-13-3 53_41-1-2-2

  11. BI-53_41-1 Wafer 5 and Wafer 6Three Good Parts 53_41-1-5-2 53_41-1-6-2 53_41-1-6-4

  12. BI-53_41-1 Wafer 5 and Wafer 6Dark current at +10C 51pA/cm2 55pA/cm2 45pA/cm2 53_41-1-5-2 53_41-1-6-2 53_41-1-6-4

  13. BI-53_41-1-6-3-IA_A Dark current at +10C IAD Damage on Panels IA_B, IA_C • Panels IA_A matches the dark current of 5-2, 6-2 and 6-4 • Used to infer charge transfer efficiency for the good devices • Minimizes risks associated with handling • Preparing for test at MIT designated clock and bias parameters 55pA/cm2 53_41-1-6-3 53_41-1-6-2 53_41-1-6-4

  14. Comparison to Past CCID41 Data CCD Dark Current vs. Temperature for Ion Implant Laser Anneal and Molecular Beam Epitaxy Processes REXIS DATA Non-Dithered Lesser REXIS DATA Non-Dithered MBE 55pA/cm2 53_41-1-6-3 53_41-1-6-2 53_41-1-6-4

  15. REXIS Electronics Bias Condition • Based on conversation with Joel Villasenor 7/24/2012 • Found it beneficial to set SCP to 14 V to clear up some flaring in the frame store • REXIS setting reduced full well capacity and dark current (as expected from theory)

  16. BI-53_41-1-6-3-IA_A MIT Parameters and Optimization • Successful operation of CCID41 using MIT’s suggested clock and bias parameters • At +10C, increasing the scupper potential helped clear up stray charge at the interface of the frame store and the serial register 55pA/cm2 Temp +10C Scupper +14V Temp +10C Scupper +12V 53_41-1-6-2 53_41-1-6-4

  17. BI-53_41-1-6-3-IA_A Fe-55, Charge Transfer Efficiency Parallel CTE = .99999 55pA/cm2 Temp +10C Scupper +14V 53_41-1-6-2 53_41-1-6-4

  18. Result Summary

  19. Future Work • Test performance of OBF test part 41-1-8-9 • +10C, -40C dark current image • Test Four 41lot1 BI devices: EM-units • +10C, 5 int. times, -40C dark current image. • Retest W5 / W6 failed parts by probing “fresh” bond-pads • CCID53_41-1-6-1 • CCID53_41-1-5-1 • Invite MIT REXIS to see our test station in action

  20. Discussion on CCD Specification Requirement • What is the required dark current in terms of e-/sec? • Integration time • Signal charge • What is the required % of area that meets this specification? • Cosmetics • What is the CTI required? • Setting these numbers will enable us to identify how many potential flight-grade chips

  21. An Example Analysis of FI Data • Took data captured on 53lot1 front-illuminated devices at 10 oC • Measured effective area with respect to given dark current criteria • 3200 e-/pix/secat 10 oC ~ 0.5 e-/pix/sec at -60 oC

  22. Thumbnails of FI Measurements

  23. Extra Slides

  24. Dependencies for D-D OBF Project Tasks completed during this update Chip-level testing 53lot1 MBE BI (16 chips) Chip-level OBF process 53lot1 MBE BI (2 chips) Test MBE chips with OBF at MKI 53lot1 MBE BI (2 chips) Chip-level OBF process 53lot1 MBE BI (6 chips) Test MBE chips with OBF at MKI 53lot1 MBE BI (6 chips) Testing set-up 41lot1 FI (4 chips) Characterize OBF at G82 Chip-level testing 41lot1 Lesser BI (11 chips) Chip-level OBF process devel. 41lot1 Lesser BI (4 chips) Legend Done In progress

  25. Dependencies for REXIS Project Wafer-level FI screening test 53lot1 FI (48 chips) Wafer-level MBE BI process 53lot1 (4 wafers) Deposit OBF 53lot1 (4 wafers) Package 53lot1 (4 chips) Deliver flight units 53lot1 (4 chips) Wafer-level MBE BI process 53lot1 (8 wafers) OBF 53lot1 (6 chips) Package 53lot1 (4 chips) Deliver flight spares 53lot1 (4 chips) Chip Testing set-up 41lot1 FI (4 chips) OBF Test results Packaging development 41lot1 FI (4 chips) Wafer Testing set-up Mechanical Monitor 53lot1 Chip-level testing 41lot1 Lesser BI (11 chips) Package for EM 41lot1 Lesser BI (4 chips)

More Related