Additional Hardware Optimization

1. RPS Additional Hardware Optimization m5151117 Yumiko Kimezawa

2. Outline RPS • Ethernet • Additional Hardware Optimization • Future Work

3. Ethernet RPS • Hardware part • Composition of necessary cores for handling Ethernet (Completion) • Compilation (Not completion) • Software part • - Changing software for transferring data with Ethernet (Not completion)

4. Ethernet RPS • Handling Ethernet is not easy • I don’t have enough time… If I have extra time, I will deal with this task

5. Proposal of Optimization RPS • Pipeline processing on single CPU • →Using hardware resources effectively • Adding DMA controller • → Data transfer is accelerated to high speed < Simple image > Signal Reading Filtering PPD Algorithm Signal Reading Filtering PPD Algorithm

6. Additional Hardware Optimization (Current Work) RPS • Change of existing hardware for executing pipeline processing • Using clock crossing bridge core • Dividing CPU memory into data memory and instruction memory • Implementing DDR2 SDRAM core instead of on-chip memory Graphic LCD LED FPGA Graphic LCD Controller LED Controller DDR2 SDRAM Timer FIR Filter ECG Data Avalon Bus Clock Crossing Bridge Data Mem Inst Mem CPU Clock Crossing Bridge SysID JTAG UART PLL

7. SOPC Builder Window RPS

8. Future Work RPS • Minor change of software having single CPU • Until Nov. 1 • Measurement of data transfer time between ECG data rom and filter, filter and memory and so on, and finding bottlenecks of data transfer • Until Nov. 8~16 • Adding DMA controller module to BANSMOM for getting rid of the bottlenecks of data transfer • Until Nov. 16~23

9. RPS • Investigation of BANSMOM System • Need to divide Master CPU memory into inst. mem and data mem • Need to use off-chip memory JTAG UART : Data flow : Control signal Graphic LCD LED FPGA Graphic LCD Controller External Memory ECG Data Slave CPU Slave CPU Memory DMA controller LED Controller Avalon Bus Timer Shared Memory Master CPU Inst Mem Data Mem FIR Filter Timer Master Module PPD Module