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I/O. 1. 24. I/O. 23. 2. 5. I/O. 6. 22. 3. 7. I/O. 8. 21. 4. 9. I/O. 10. 5. 20. 11. I/O. 12. 6. 19. 13. I/O. 18. 14. 7. 15. I/O. 16. 8. 17. 17. RD. 9. 18. 16. 19. WR. 10. 15. 20. 21. TXE. 11. 22. 14. 23. RXF. 12. 13. 24. 25. 26. 27. 28. 29.
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I/O 1 24 I/O 23 2 5 I/O 6 22 3 7 I/O 8 21 4 9 I/O 10 5 20 11 I/O 12 6 19 13 I/O 18 14 7 15 I/O 16 8 17 17 RD 9 18 16 19 WR 10 15 20 21 TXE 11 22 14 23 RXF 12 13 24 25 26 27 28 29 30 31 32 33 34 5 6 Pin-Outs for Additional Hardware 7 DLP-USB245M Pins 13-24 are connected to FPGA pins 7 through 18 of connector A1 First 30 pins from connector A2 Second 2 pins from connector A1
Input Conditioning (Serial to Parallel Conversion)
Output Conditioning (Parallel to Serial Conversion)