A Probabilistic Method to Determine the Minimum Leakage Vector for Combinational Designs

1. A Probabilistic Method to Determine the Minimum Leakage Vector for Combinational Designs Kanupriya Gulati Nikhil Jayakumar Sunil P. Khatri Department of Electrical & Computer Engineering Texas A&M University, College Station, TX-77843

2. Motivation • Sub Threshold Leakage Current (Ids) • Magnitude of ‘Leakage Currents’ depend on the ‘Input Vector’. Leakage of a NAND3 gate • Hence it is desirable to set every gate to its minimal leakage state. • Not always possible • Logical inter-dependencies of the gates’ inputs. • Finding the input vector to minimize the circuit leakage : • Input Vector Control (IVC).

3. Overview of our Approach • First compute signal probabilities for all nodes assuming primary input signal probabilities are 0.5. • Heuristically adjust for reconvergence. • Select best “candidate” gate to set to low leakage state in a given iteration. • Gate that is probabilistically most likely to result in the largest leakage reduction. • Assign the selected gate its best state, such that the leakage of the selected gate is probabilistically minimized. • All other gates which are newly implied by the state just selected are accounted for when making this decision.

4. Overview of our Approach • Check if the logic values set when setting a gate to its low leakage state are satisfiable. • Call a SAT solver every p iterations. • Undo assignments in last p iterations if unsatisfiable and make a different selection for the iteration that caused unsatisfiable condition. • After any iteration, adjust gate probabilities to account for nodes whose logic values have been set. • Fixed number of passes made for the circuit with above steps applied succesively. • Each pass is more “lenient” in setting a node to a logic value v when its signal probability deviates from v. • Last pass is most lenient – allows any deviation from v to be accepted.

5. Adjustment Heuristic for Reconvergent Fanouts 0.75 0.1875 0.25 P(Z) = 0.1875 0.25 • Propagate probabilities assuming P(X) = 0 and P(X) = 1 to calculate reconvergence adjustment factor. P(Z)new = 0 ZAdj Factor = P(Z)new - P(Z) = - 1 P(Z) P(Z)adj = P(Z) * (1+ZAdj Factor)

6. Finding Best Candidate Gate • Find best candidate gate whose input we would like to finalize. • Rank gates by probability criterion C. • Gates with high probability of being in a high leakage state are assigned a higher rank. pi – probability that gate is in state i li – leakage in state i limax – maximum leakage of the gate limin – minimum leakage of the gate • (limax – limin) term ensures that gates with large leakage ranges are favored. • Choose gate with highest C.

7. Finding Best Leakage State • Finding the best (minimum) leakage state for selected gate G. • Account for leakages for all gates n whose states become fully assigned due to assigning of the state of G. dj – deviation of values assigned to gate inputs from their probabilistic values. lj – leakage in state j j – set of states of all gates that are fully assigned - Modified formula for L to allow biasing towards lower leakage (use higher β) or towards lower deviation (use higher γ)

8. Accepting Leakage States and Endgame • Accepting the State Assignment • Test if implications of assignment are within a margin(mi). • - say mi = 0.5, probability = 0.3 and implied node value is logic 1. • Then (1-0.3) > mi, hence reject assignment. • Test if the circuit with these assignments is satisfiable. • Update probabilities of allgates affected. • Until the SAT solver sanctions these assignments, • labeled as gold_value, and • then platinum_value. • Over iterations the margin (mi) for accepting an assignment is relaxed. • Stop when all primary inputs have been assigned a state. • Implied node probabilities are adjusted to reflect newly computed implications. • If node is set to 1, probability is set to (1-α). • If node is set to 0, probability is set to α.

9. Experimental Setup • Used MCNC 91 benchmark designs using 0.1μ library with 13 gates. • Number of inputs (library gates) between 1 & 4. • Ran technology independent logic optimizations (script_rugged in SIS). • Mapped them for delay. • PLmin technique is implemented in SIS. Tried the following 3 methods. Commonly used Figure of Merit: Our new Figure of Merit:

10. Results - Small circuits Exhaustive and Estimated Leakages for small circuits in nA. • For small circuits the minimum and maximum leakage values were found • through exhaustive simulation of all primary input vectors.

11. Results – Large Circuits For large circuits, the minimum and maximum leakage values were found by simulating 10000 distinct random input vectors.

12. Conclusions • Developed a probabilistic method to determine IVC. • Method is fast, flexible and provides accurate results. • For small examples, found leakage values 5.3% off from minimum leakage (exact). • For large examples, found leakage values 3.7% off the minimum leakage (random 10,000 vectors). • Runtimes of the method are much lower than existing techniques which produce similar quality results.

13. Results - Large circuits Leakage for Large Circuits in nA

14. Algorithm for determining IVC: … (contd)

15. Algorithm for determining IVC: (contd)