A Self-adjusting Scheme to Determine Optimum RBB by Monitoring Leakage Currents

1. A Self-adjusting Scheme to Determine Optimum RBBby Monitoring Leakage Currents Nikhil Jayakumar* Sandeep Dhar$ Sunil P. Khatri* $National Semiconductor, Longmont,CO. *Texas A&M University, College Station, TX.

2. Introduction • Leakage power is expected to exceed dynamic power consumption in the near future. • Existing techniques to reduce leakage • Static • High VT power gating switches (MTCMOS, HL). • Dual VT assignment (DUET). • Dynamic • DTMOS, SCCMOS. • Reverse Body Biasing (RBB). • RBB reduces leakage (body effect) but if RBB istoo high, leakage can actually increase due toother leakage components.

3. Leakage Components • Sub-threshold leakage • Drain -> Source • Gate leakage • Drain -> Gate / Source -> Gate • Drain -> bulk leakage • Bulk Band to Band Tunneling (BTBT) • Surface BTBT (Gate Induced Drain Leakage - GIDL) • Reverse biased PN junction current

4. Effect of RBB on Leakage • Sub-threshold decreases exponentially with Vt, which increases with RBB. • Gate leakage (drain-gate) does not change appreciably with RBB. • At RBB BTBT dominates GIDL. • Mainly, sub-threshold leakage & BTBT change with RBB. • Sub-threshold leakage decreases with RBB,while BTBT increases with RBB. • Hence there exists an optimum RBB point for minimum leakage.

5. Variation in Leakage Components with RBB Plot of leakage current components with RBB as measured on a large NMOS device on a test-chip at 25oC

6. Optimal RBB Determination – Previous work • In “Optimal Body Bias Selection for Leakage Improvement and Process Compensation over Different Technology Generations” – C. Neau and K. Roy (ISLPED03), a circuit is presented to help find the optimal RBB. • Based on the assumption that sub-threshold leakage is negligible compared to BTBT for stacked devices. • Claims that optimal RBB is at point at which leakage through 2 stacked devices is equal to half the leakage through a single leaking device. • This assumption underestimates the sub-threshold leakage component.

7. Optimum RBB • Point A marks the optimum RBB point as would be suggested by the previous scheme. • Point B marks the actual optimum RBB. • This work proposes a circuit which dynamically finds point B. Leakage current measured for a large NMOS device and 2 large NMOS devices in series on a 0.13μtest-chip at 25oC

8. Leakage Monitoring and Self-adjusting Scheme • The Leakage Monitoring Scheme consistsof 3 components • A Leakage Current Monitor (LCM). • This leakage monitor is designed to work over a wide range of leakage currents. • A Digital Block to interface with the LCM and control the body-bias voltage. • A programmable body bias voltage generator controlled by the Digital Block. • We discuss the first 2 blocks.

9. Leakage Monitoring and Self-adjusting Scheme • The Leakage-Monitoring scheme is based on measuring the time taken for a leaking device to discharge (or charge) a capacitive load. • At the heart of this is the LCM.

10. The Leakage Current Monitor (LCM) • Shown here: LCM for NMOS leakage. • Node Nchk is initially precharged. • Leakage through a representative device ML is measured by sampling node Nchk at regular intervals and seeing when (number of sampling periods after which) the node Nchk is discharged. • A capacitor bank and a small gate bias are provided to increase or decrease rate of discharge of the node. • Allows the LCM to work over a wide range.

11. We start at a point on the curve where leakage will decrease with RBB We then move along the curve till … we hit the point at which leakage starts increasing Operation of the Scheme • The Digital Block measures the time taken for the leaking device in the LCM to discharge (charge) the monitored node in the LCM.

12. Salient features of our Scheme • Low power • Only about 11.4μA at 1.2V and 125oC for 0.13 μm TSMC process • Leakage current measurement based on time taken to discharge a node. • Uses same leakage monitoring cell to handle large variations of leakage currents • Capacitor bank and switch-able gate bias used to adjust range.

13. Area required • Layout (standard cell based) done for the leakage monitors for PMOS and NMOS. • Height of standard cell = 3.285μ. • Width of cell for • Pulse generator = 38.22μ (126 μ2) • LCM nmos = 77.87μ (256 μ2) • LCM pmos = 86.41μ (284 μ2) • Total area approx = 665 μ2

14. Conclusion • Reverse body biasing is a useful technique toreduce leakage. • However, if the RBB is too high, the leakagecurrent may inadvertently increase. • The optimum RBB point can vary with processand temperature variations. • Hence a scheme such as ours that can dynamically find the optimum RBB point can help greatly. • Also the scheme itself does not consume veryhigh power and it has a very modest silicon area requirement.

15. Questions ?