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A Heuristic to Determine Low Leakage Sleep State Vectors for CMOS Combinational Circuits

A Heuristic to Determine Low Leakage Sleep State Vectors for CMOS Combinational Circuits. University of Michigan, IBM ICCAD ‘03. Outline. Introduction Previous Related Work Terminology Heuristic Approach Results Conclusions. Low Vt logic module. Virtual ground. sleep. high Vt.

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A Heuristic to Determine Low Leakage Sleep State Vectors for CMOS Combinational Circuits

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  1. A Heuristic to Determine Low Leakage Sleep State Vectors for CMOS Combinational Circuits University of Michigan, IBM ICCAD ‘03

  2. Outline • Introduction • Previous Related Work • Terminology • Heuristic Approach • Results • Conclusions

  3. Low Vt logic module Virtual ground sleep high Vt Introduction • Bellow .13 process leakage dominates power consumption • Leakage power = exp(-q*Vt / K*T) • Leakage reduction methods • Dual Vt partition • MTCMOS • State assignment • Gate leakage current depend on input state

  4. assign “1” : sleep PI PO Combinational Logic gated clock clock FF/ Latch PPI sleep sleep assign “0” : clock sleep Works on State Assignment • When clock disable circuits in standby mode while power still turn on • Maintain the last state when active V.S. assign new low leakage state when sleep

  5. P0 N5 C0 Z0 C4 P2 N6 C1 P3 N7 P1 C2 Z1 C5 C3 P4 N8 Terminology - CC0,CC1 • Controllability – provide guidance in ATPG • Difficulty of setting a signal to 0 or 1 as CC0,CC1 • Use functionality to get controllability and its list

  6. best condition(x0) minimum leakage worst condition(11) max leakage Terminology – BIC,WIC • Best and worst input condition (BIC)(WIC) • NAND gate for example: • (x,0) state makes minimum leakage of NAND2 • (1,1) state makes maximum leakage of NAND2

  7. P0 N5 C0 Z0 C4 P2 N6 C1 P3 N7 P1 C2 Z1 C5 C3 P4 N8 Terminology – BIC,WIC • Use CC list to build constraint list

  8. Terminology – D,C cells • Dominated and conflicting cells • P’s min cost state forces Q into min cost state • P’s min cost state violates Q’s min cost state

  9. Terminology – Cost Function • Cost function • NAND2 penalty for example • CLP(Nand2) = 0.5*(L01+L11-L00-L10) • WLP(Nand2) = L11-0.5*(L00+L10) Cost(Ci) = ∑ (CLP(conflicting cells(Ci))) – ∑(CLP(dominated cells (Ci))) – CLP(Ci)

  10. mini cost 1 2 3 x1000 x1x0x x100x - C0, C3, C5 C3, C5 C4 C0 C3 Heuristic Approach (1/2) Controllability List Constraint List Conflicting & Dominated cell All cells in selection list C2 C5 1.rm dominated cells 2.store conflicting cells 3.update list

  11. Heuristic Approach (2/2) • For any undefined input signal i • Set i to 1 or 0 based on cost_input(i) • Cost_input(i) = ∑(WLP( WIC satisfied cells )) • Attempt to minimize the occurrence of WIC • Low leakage input state is ready

  12. Result Random (mA) Heuristic (mA) Diff % Runtime Saving(x) • Max 5% degradation • Max 10% better

  13. Conclusion • Use controllability and functional dependency to solve input vector search efficiently • The results based on good heuristic can be very close to exhaustive search

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