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Contents of the Lecture

Contents of the Lecture. 1. Introduction 2. Methods for I/O Operations 3. Buses 4. Liquid Crystal Displays 5 . Other Types of Displays 6 . Graphics Adapters 7 . Optical Discs . 6 . Graphics Adapters. Structure of a Graphics Adapter Color Representation Video Memory

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Contents of the Lecture

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  1. Contents of the Lecture • 1. Introduction • 2. Methods for I/O Operations • 3. Buses • 4. Liquid Crystal Displays • 5. Other Types of Displays • 6. Graphics Adapters • 7. Optical Discs Input/Output Systems and Peripheral Devices (06-1)

  2. 6. Graphics Adapters • Structure of a Graphics Adapter • Color Representation • Video Memory • Graphics Accelerators • 3D Accelerators • Graphics Processing Units • Digital Interfaces for Monitors Input/Output Systems and Peripheral Devices (06-1)

  3. Structure of a Graphics Adapter (1) Input/Output Systems and Peripheral Devices (06-1)

  4. Structure of a Graphics Adapter (2) • Graphics Controller • Implements the main functions of the graphics adapter • System Bus Interface • Transfers in burst mode • Transfers with no wait states when reading the video memory • FIFO memory for efficient write to the video memory Input/Output Systems and Peripheral Devices (06-1)

  5. Structure of a Graphics Adapter (3) • Video Memory Interface • Allows to update the video images • VGARegisters and Control Registers • Enable programming of the video adapter for operation in VGA modes • There are adapters that are no longer compatible with the VGA standard • Cursor Generator • Graphic Functions • Implemented by graphics accelerators Input/Output Systems and Peripheral Devices (06-1)

  6. Structure of a Graphics Adapter (4) • Video BIOS • Providesvideo functions for access to the graphics adapter • The BIOS programs of different adapters are different difficult programming • VESA (Video Electronics Standards Association) standard for high-resolution BIOS functions • Video Memory • Holds the video image frame buffer Input/Output Systems and Peripheral Devices (06-1)

  7. Structure of a Graphics Adapter (5) • RAMDAC Circuit (RAMDAC – RAMDigital to Analog Converter) • Reads the digital image and converts it intoanalog signals • The RAMDAC functions may be integrated into the graphics controller • Only required for displays with analog inputs • Displays that operate in the digital domain reconvert the analog signals to digital form Input/Output Systems and Peripheral Devices (06-1)

  8. Structure of a Graphics Adapter (6) • CRT Controller (CRT – Cathode Ray Tube) • Generates the synchronization signals required for displaying the images by a CRT monitor: SH, SV • Clock Generator • Converts the quartz oscillator frequency to the frequencies needed for the graphics controller, CRT controller, and RAMDAC circuit Input/Output Systems and Peripheral Devices (06-1)

  9. Structure of a Graphics Adapter (7) • Video Ports • Enable to transfer the video images to a monitor • There are several variants of video ports • VGA(Video Graphics Array) • Analog interface • Designed for CRT displays, but also used by some liquid crystal displays • Electrical noise may occur • DB-15 connector Input/Output Systems and Peripheral Devices (06-1)

  10. Structure of a Graphics Adapter (8) • VIVO (Video In Video Out) • Analog interface for connecting to TV sets, DVD players, game consoles (TV Out) • Signals: S-Video (Y/C); composite video; component video (e.g., RGB) • 9-pin mini-DIN connector • DVI (Digital Visual Interface) • Digital interface • DVI-I (digital and analog signals) or DVI-D (digital signals only) connector Input/Output Systems and Peripheral Devices (06-1)

  11. Structure of a Graphics Adapter (9) Video adapter with VGA, VIVO, and DVI ports Input/Output Systems and Peripheral Devices (06-1)

  12. Structure of a Graphics Adapter (10) • HDMI (High-Definition Multimedia Interface) • Digital interface for uncompressed video data • Allows to send digital audio data over the same cable • 19-pin (single-link) or 29-pin (dual-link) connector • DisplayPort • Digital interface for video and audio data • Targeted to replace the VGA and DVI interfaces • 20-pin connectors for 1, 2, or 4 lanes Input/Output Systems and Peripheral Devices (06-1)

  13. 6. Graphics Adapters • Structure of a Graphics Adapter • Color Representation • Video Memory • Graphics Accelerators • 3D Accelerators • Graphics Processing Units • Digital Interfaces for Monitors Input/Output Systems and Peripheral Devices (06-1)

  14. Color Representation (1) (a) • 8 bits to represent a pixel color • Pseudo-color mode • 256 colors • A RAM CLUT(Color Look-Up Table) is used to extend the number of colors Input/Output Systems and Peripheral Devices (06-1)

  15. Color Representation (2) (b) • 15 bits for each pixel • 32,768 colors • In the video memory, 16 bits are allocated for each pixel • 5 bits for each primary color Input/Output Systems and Peripheral Devices (06-1)

  16. Color Representation (3) (c) • 16 bits for each pixel • 65,536 colors • 6 bits are allocated for the green color • 5 bits are allocated for each of the red and blue colors • High Color mode Input/Output Systems and Peripheral Devices (06-1)

  17. Color Representation (4) (d) • 32 bits for each pixel • The 8 MSBs are not used • 16,777,216 colors • Un-compacted pixel mode • Allows to simplify the adapter structure • Reduces the efficiency of memory use Input/Output Systems and Peripheral Devices (06-1)

  18. Color Representation (5) (e) • 24 bits for each pixel • 16,777,216 colors • Compacted pixel mode • The video memory is used more efficiently • Reduces the required transfer rate • (d), (e): True Color modes Input/Output Systems and Peripheral Devices (06-1)

  19. 6. Graphics Adapters • Structure of a Graphics Adapter • Color Representation • Video Memory • Graphics Accelerators • 3D Accelerators • Graphics Processing Units • Digital Interfaces for Monitors Input/Output Systems and Peripheral Devices (06-1)

  20. Video Memory (1) • Video memories can be single-ported or dual-ported • Single-ported video memory • The unique data port is used torefresh the screenand towrite new data by the CPU or graphics controller • The operations cannot be performed in parallel • The transfer rate must be enough for all these operations Input/Output Systems and Peripheral Devices (06-1)

  21. Video Memory (2) Placement of a single-ported video memory Input/Output Systems and Peripheral Devices (06-1)

  22. Video Memory (3) • Dual-ported video memory • One of the ports is used to update the images in memory • The second port has serial accessand is used to refresh the images on the screen • Memory update and screen refresh can be performed in parallel • An external RAMDAC circuit is needed Input/Output Systems and Peripheral Devices (06-1)

  23. Video Memory (4) Placement of a dual-ported video memory Input/Output Systems and Peripheral Devices (06-1)

  24. Video Memory (5) • Video Memory Size • Determines themaximum resolution andnumber of colors that can be displayed • The required memory size is: S = (RX RYBpp)/8 RX, RY – no. of pixels horizontally/vertically Bpp– no. of color bits per pixel • A larger video memory is required 3Daccelerators Input/Output Systems and Peripheral Devices (06-1)

  25. Video Memory (6) • Video Memory Transfer Rate • The maximum transfer rate bandwidth • Affected by video memorytechnology and access time • Bandwidth has to be shared by: screen refreshing circuits, CPU, graphics controller • 30 .. 50% of the bandwidth should be reserved for other functions, different than refreshing Input/Output Systems and Peripheral Devices (06-1)

  26. Video Memory (7) • DDR-400(PC3200) memory • Maximum transfer rate: 3,200 MB/s • Average transfer rate: ~1,600 MB/s • DDR2-667(PC2-5300) memory • Maximum transfer rate :5.336 GB/s • DDR3-1600 (PC3-12800) memory • Maximum transfer rate : 12.8 GB/s • DDR4-2400 (PC4-19200) memory • Maximum transfer rate : 19.2 GB/s Input/Output Systems and Peripheral Devices (06-1)

  27. Video Memory (8) • GDDR (Graphics Double Data Rate) • Designed by ATI Technologies with the collaboration of the JEDEC committee • Several versions: GDDR2 .. GDDR5 • GDDR2 and GDDR3: based on DDR2 technology • GDDR4 and GDDR5: based on DDR3 technology • Low voltage: 1.8 V .. 1.5 V  reduced power consumption and heat output • Separate data strobe signals for read and write Input/Output Systems and Peripheral Devices (06-1)

  28. Video Memory (9) • GDDR5 • Combines high performance with stable operation and low implementation costs • Memory organization: 32 • Differential command clock signal (CK, CK#) • Two diff. write clock signals (WCK, WCK#) • Two data bytes are aligned to one WCK signal • Example for a data rate of 5 Gbits/s: • fCK = 1.25 GHz; fWCK = 2.5 GHz Input/Output Systems and Peripheral Devices (06-1)

  29. Video Memory (10) • Data bus inversion • Reduces the number of zero bits transmitted • Indicated with a DBI# signal for each byte • Transmission lines have high level termination  power dissipation is reduced • Address bus inversion • Signal training • Phase adjustment of clock, data, and address signals Input/Output Systems and Peripheral Devices (06-1)

  30. Video Memory (11) • Address training: alignment of the address bus to the CK clock signal • Alignment of WCK signal to the CK signal • Data training: alignment of the data lines to the corresponding WCK signal • A “hidden” data re-training is possible • Calibration: improves the reliability • Auto-calibration: drive strength, termination impedance • Software-controlled adjustment Input/Output Systems and Peripheral Devices (06-1)

  31. Video Memory (12) • Burst read/write access to the internal memory: 8 bits/pin  256 bits (two CK cycles) • Maximum transfer rates of 4 .. 7 Gbits/s per pin  16 .. 28 GB/s for 32 pins • Error detection • Dedicated EDC (Error Detection Code) pins for sending CRC codes to the controller • CRC code: for each data byte + DBI# line • Allows to detect single-bit and double-bit errors Input/Output Systems and Peripheral Devices (06-1)

  32. Video Memory (13) • Power management • Features that allow to consume power only when it is needed • Scalable clock frequency and data rate: 5 Gbits/s .. 200 Mbits/s • Low power mode for the DRAM core • Multiple levels for termination impedance: increasing the impedance at slower data rates • Low supply voltage: 1.5 V • Data and address bus inversion Input/Output Systems and Peripheral Devices (06-1)

  33. 6. Graphics Adapters • Structure of a Graphics Adapter • Color Representation • Video Memory • Graphics Accelerators • 3D Accelerators • Graphics Processing Units • Digital Interfaces for Monitors Input/Output Systems and Peripheral Devices (06-1)

  34. Graphics Accelerators (1) • Contain specialized circuits to execute the mathematical operations required for graphics rendering • Release the CPU from the task of executing these operations • The first graphics accelerators: AVGA (Accelerated VGA)adapters • Subsequent graphics accelerators: 2Daccelerators • The linkbetween the accelerator circuitry and the OS is made via a driver Input/Output Systems and Peripheral Devices (06-1)

  35. Graphics Accelerators (2) • Common 2D graphics functions: • BitBlt (BitBlock Transfer) • Two bitmaps are combined with a raster operation  Boolean operator • The result is transferred to the destination area • Blitter: dedicated circuit for the BitBlt operation • Tracing lines, drawing rectangles, circles • Filling surfaces or polygons • Adding color Input/Output Systems and Peripheral Devices (06-1)

  36. Graphics Accelerators (3) • Multimedia accelerators: graphics accelerators extended with audio and video acceleration functions • Functions: • Decoding audio data streams • Scaling video images in x, y directions • Converting digital video signals into RGB signals • Decompressing video images represented in various formats Input/Output Systems and Peripheral Devices (06-1)

  37. 6. Graphics Adapters • Structure of a Graphics Adapter • Color Representation • Video Memory • Graphics Accelerators • 3D Accelerators • Graphics Processing Units • Digital Interfaces for Monitors Input/Output Systems and Peripheral Devices (06-1)

  38. 3D Accelerators • 3D Accelerators • The Need for 3D Accelerators • 3D Images • 3D Operations Input/Output Systems and Peripheral Devices (06-1)

  39. The Need for 3D Accelerators • The monitor screen is two-dimensional  the images displayed must be two-dimensional • To display 3D objects, they must be converted into 2D images • Complex computations are needed to translate 3D images into 2D images • A 3D accelerator allows the programs to display virtual 3D images with a high level of details Input/Output Systems and Peripheral Devices (06-1)

  40. 3D Accelerators • 3D Accelerators • The Need for 3D Accelerators • 3D Images • 3D Operations Input/Output Systems and Peripheral Devices (06-1)

  41. 3D Images (1) • Are managed usingabstract models • An object is represented as a set of points defined by its x, y, and z coordinates  position of vertices • If the object vertices are connected with lines, surfaces are obtained  can be filled with a certain color or texture • Each 3D object is composed of a large number of triangles(or polygons) that describe its surface Input/Output Systems and Peripheral Devices (06-1)

  42. 3D Images (2) • Animated 3D graphics requires to perform a series of geometry computations that define the position of objects in 3D space • The geometry computations that handle the vertices of triangles can be performed by the CPU or by the graphics processor • The graphics processor must convert these triangles into solid surfaces intensive computations are needed Input/Output Systems and Peripheral Devices (06-1)

  43. 3D Images (3) • In the real world, objects interact with each other • Complex mathematical equations are used to determine whether an object is visible in a scene from a given angle • Besides the color components, for each pixel an alpha value must also be stored • Indicates the degree of transparency of the pixel in the final image Input/Output Systems and Peripheral Devices (06-1)

  44. 3D Images (4) • Another information that must be stored: the depth in space or zcoordinate • The accelerator determines thez value of the objects’ pixels in a plane and displays those with a smaller z value • The pixels’ depth information is stored in a separate buffer z-buffer • Usually, 32 bits are allocated in thez-buffer for each pixel Input/Output Systems and Peripheral Devices (06-1)

  45. 3D Images (5) • Each time the image is updated, the color and depth of pixels must be recomputed • Applying different 3D computations to the scene process of rendering • Fills in all of the points on the surface of the object that previously was stored only as a set of vertices • A solid object with 3D effects will be drawn on the monitor Input/Output Systems and Peripheral Devices (06-1)

  46. 3D Accelerators • 3D Accelerators • The Need for 3D Accelerators • 3D Images • 3D Operations Input/Output Systems and Peripheral Devices (06-1)

  47. 3D Operations (1) • 3D operations are performed in two stages: • Geometry stage: clipping, transformation, lighting • Rendering stage: shading, texture mapping with adding the perspective effect, texture filtering, alpha blending • On current 3D accelerators, operations in both stages are performed by the graphics processor Input/Output Systems and Peripheral Devices (06-1)

  48. 3D Operations (2) Input/Output Systems and Peripheral Devices (06-1)

  49. 3D Operations (3) • Clipping • Determines what part of an object is visible on the screen • Transformation • Translation; reflection; glide reflection; scaling • Lighting • Lighting effects create color shading, light reflection, shadows Input/Output Systems and Peripheral Devices (06-1)

  50. 3D Operations (4) • Tessellation • Dividing polygons into smaller structures for rendering; triangles may be used • Shading • Enables to better define the shape of an object • Texture Mapping • Adding surface details (textures) to polygons that represent objects Input/Output Systems and Peripheral Devices (06-1)

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