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Test Setup for FE-I3 single chips / modules, FE-I4_proto1 and for full scale FE-I4

Test Setup for FE-I3 single chips / modules, FE-I4_proto1 and for full scale FE-I4. Marlon Barbero, Bonn. USBPix – Lightweight USB based DAQ System for FE-I3 / FE-I4. USB Controller. SRAM. FPGA. AC coupling. single chip card con. type-0 connector. Multi-IO USB/FPGA Board.

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Test Setup for FE-I3 single chips / modules, FE-I4_proto1 and for full scale FE-I4

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  1. Test Setup for FE-I3 single chips / modules, FE-I4_proto1 and for full scale FE-I4 Marlon Barbero, Bonn

  2. USBPix – Lightweight USB based DAQ System for FE-I3 / FE-I4 H. Krüger, ATUW, NIKHEF, 6.11.08

  3. USB Controller SRAM FPGA AC coupling single chip card con. type-0 connector Multi-IO USB/FPGA Board Quad Module Adapter Card H. Krüger, ATUW, NIKHEF, 6.11.08 FE-I3 Module with Flex Adapter

  4. USB based FE-I3 Readout System - USBPixBoard • Lightweight “Replacement” for the TurboPLL/PCC • (Re)use TurboDAQ software ? • Hardware based on FPGA card with USB interface • Supports up to four single chips or four FE modules • AC coupling for SP operation of modules H. Krüger, ATUW, NIKHEF, 6.11.08

  5. reset/sync state machine SYNC RST scan routines write data buffer (parser) configuration state machine LD DI CCK external trigger 8051 µC strobe & LV1 state machine LV1 master state machine STRB USB data receiver state machine read data buffer & event builder DO1 DO2 clock histogramming state machine XCK full chip scan data: 2880px  256 steps  8bit data USB controller data memory FPGA external Firmware Structure H. Krüger, ATUW, NIKHEF, 6.11.08

  6. USBPixBoard – Some Specs • USB/FPGA Board (S3MultiIOBoard) • 15 Mbyte/sec FPGA  PC data transfer • 2 Mbyte SRAM (sufficient for full single chip histogram) • Xilinx XC3S1000 FPGA • LVDS and TTL IOs (for ext. trigger, TDC etc.) • 8051 USB microcontroller • Drivers for Windows XP and Linux • Module Adapter Card • four channels support single chip cards or modules • serial powering option for modules • current and (individual) voltage measurement for SP • “Lightweight”/low-cost replacement for TPLL/TPCC • limited FPGA/memory resources: no DSP, no dedicated, programmable delay lines H. Krüger, ATUW, NIKHEF, 6.11.08

  7. USBPixBoard – Status • Target: FE-I3 single chip, (FE-I4 proto 1), FE-I4 ‘full chip’ • Hardware • prototype HW, production of ~20 boards planned • FPGA + µC firmware and DLL programming  UBonn • Software • Based on DLL with low-level functions + GUI (two options): • Modified TurboDAQ software  UGöttingen, Jörn Grosse-Knetter • New PixLib based SW development (C++, QT for Win & Linux), “open source”, access via version control system and Wiki pages: http://icwiki.physik.uni-bonn.de/twiki/bin/view/Systems/WebHome#UsbPix H. Krüger, ATUW, NIKHEF, 6.11.08

  8. FE-I4_proto1 test setup

  9. FE-I4_proto1 test setup

  10. Software

  11. Interface Disabled!

  12. Parametric scan Threshold Noise

  13. Addressing new Inject Hitmap Filter interesting hit and do the math

  14. Status • MUX arrived last week • were installed successfully • Test without FE good! • FEI4_proto1 connected to Testboard • Due to bad connection so pins had to be bend up Plans: • Finish Software development  start characterization. • Should submit new version of test board with proper MUX connection.

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