Review of TigerSHARC Processor Operations

1. This presentation will probably involve audience discussion, which will create action items. Use PowerPoint to keep track of these action items during your presentation • In Slide Show, click on the right mouse button • Select “Meeting Minder” • Select the “Action Items” tab • Type in action items as they come up • Click OK to dismiss this box • This will automatically create an Action Item slide at the end of your presentation with your points entered. Overview of TigerSHARC processorADSP-TS101 Compute Operations Steve Daeninck,Electrical and Computer Engineering, University of Calgary, Alberta, Canada smithmr @ ucalgary.ca

2. To be tackled today • Reference sources • Register file and operations • ALU operations • MAC operations (Multiply and accumulate) • SHIFTER operations • Common errors • Example exercises ENEL 619.23 -- Review of TigerSHARC Processor

3. Reference Sources • ADSP-TS101 TigerSHARC Processor Programming Reference, Analog Devices web site. • ADSP-TS101 TigerSHARC Hardware Reference, Analog Devices web site. • ENEL619.23 Course, Reference and Laboratory Notes. ENEL 619.23 -- Review of TigerSHARC Processor

4. Register File and COMPUTE Units • Key Points • Each block can load/store 4x32bit registers in a cycle. • 4 inputs to Compute block, but only 3 Outputs to Register Block. • Highly parallel operations UNDER THE RIGHT CONDITIONS ENEL 619.23 -- Review of TigerSHARC Processor

5. Register File - Syntax XR7 -> 1x32 bit word XLR7:6 -> 1x64 bit word XFR1:0 -> 1x40 bit float XSR3:2 -> 4x16 bit words Multiple of 2 XBR3:0 -> 16x8 bit words Multiple of 4 • Key Points • Each Block has 32x32 bit Data registers • Each register can store 4x8 bit, 2x16 bit or 1x32 bit words. • Registers can be combined into dual or quad groups. These groups can store 8, 16, 32, 40 or 64 bit words. Register Syntax ENEL 619.23 -- Review of TigerSHARC Processor

6. Register File – BIT STORAGE ENEL 619.23 -- Review of TigerSHARC Processor

7. Volatile Data Registers • Volatile registers – no need to save • 24 Volatile Data registers in each block • XR0 – XR23 • YR0 – YR23 • 2 ALU summation registers in each block • XPR0, XPR1, YPR0, YPR1 • 5 MAC accumulate registers in each block • XMR0 – XMR3, YMR0 – YMR3 • XMR4, YMR4 – Overflow registers ENEL 619.23 -- Review of TigerSHARC Processor

8. Arithmetic Logic Unit (ALU) • 2x64 bit input paths • 2x64 bit output paths • 8, 16, 32, or 64 bit addition/subtraction - Fixed-point • 32 or 64 bit logical operations - fixed-point • 32 or 40 bit floating-point operations ENEL 619.23 -- Review of TigerSHARC Processor

9. Sample ALU Instruction Example of 16 bit addition XYSR1:0 = R31:30 + R25:24 Performs addition in X and Y Compute Blocks ENEL 619.23 -- Review of TigerSHARC Processor

10. Sample ALU Instructions Fixed-Point Floating-Point ENEL 619.23 -- Review of TigerSHARC Processor

11. Example int x_two = 64, y_two = 16; int x_three = 128, y_three = 8; int x_four = 128, y_four = 8; int x_five = 64, y_five = 16; int x_odd = 0, y_odd = 0; int x_even = 0, y_even = 0; x_odd = x_five + x_three; x_even = x_four + x_two; y_odd = y_five + y_three; y_even = y_four + y_two; XR2 = 64;; XR3 = 128;; XR4 = 128;; XR5 = 64;; YR2 = 16;; YR3 = 8;; YR4 = 8;; YR5 = 16;; XYR1:0 = R5:4 + R3:2;; //XR1 = x_odd, XR0 = x_even //YR1 = y_odd, YR1 = y_even ENEL 619.23 -- Review of TigerSHARC Processor

12. Multiplier • Operates on fixed, floating and complex numbers. • Fixed-Point numbers • 32x32 bit with 32 or 64 bit results • 4 (16x16 bit) with 4x16 or 4x32 bit results • Data compaction inputs – 16, 32, 64 bits, outputs 16, 32 bit results • Floating-Point numbers • 32x32 bit with 32 bit result • 40x40 bit with 40 bit result • Complex Numbers • 32x32 bit with results stored in MR register • Fixed-point only ENEL 619.23 -- Review of TigerSHARC Processor

13. Multiplier XR0 = R1*R2;; XR1:0 = R3*R5;; XMR1:0 = R3*R5;; //uses XMR4 overflow XR2 = MR3:2, XMR3:2 = R3*R5;; XR3:2 = MR1:0, XMR1:0 = R3*R5;; XFR0 = R1*R2;; XFR1:0 = R3:2*R5:4;; //40 bit multiply //32 bit mantissa ENEL 619.23 -- Review of TigerSHARC Processor

14. Multiplier XR5:4 = R1:0*R3:2;;(16 bit results) XR7:4 = R3:2*R5:4;; (32 bit results) XMR1:0 += R3:2*R5:4;;(16 bit results) XMR3:0 += R3:2*R5:4;; (32 bit results) XR3:2 = MR3:2, XMR3:2 = R1:0*R5:4;;(16 bit results) XR3:0 = MR3:0, XMR3:0 = R1:0*R5:4;; (32 bit results) ENEL 619.23 -- Review of TigerSHARC Processor

15. Practice Examples Convert from “C” into assembly code – use volatile registers long int value = 6; long int number = 7; long int temp = 8; value = number * temp; float value = 6; float number = 7; long int temp = 8; value = number * temp; ENEL 619.23 -- Review of TigerSHARC Processor

16. Avoiding common design errors float value = 6.0; float number = 7.0; long int temp = 8; value = value + (float) 1; number = number + (float) 2; temp = (int) (value + number); XR12 = 6.0;; XR13 = 7.0;; XR18 = 8;; XR0 = 1.0;; XR1 = 2.0;; XFR12 = R12 + R0;; XFR13 = R13 + R1;; XFR14 = R12 + R13;; XR18 = FIX FR14;; ENEL 619.23 -- Review of TigerSHARC Processor

17. Avoiding common design errors Convert from “C” into assembly code – use volatile registers float value = 6.0; float number = 7.0; long int temp = 8; value = number * (float) temp; XR12 = 6.0;; //valueF12 XR13 = 7.0;;//numberF13 XR18 = 8;; //tempR18 //(float)tempR18 XFR18 = FLOAT R18;; //valueF12 = numberF13 * tempF18 XFR12 = R13 * R18;; ENEL 619.23 -- Review of TigerSHARC Processor

18. Shifter Instructions • 2x64 bit input paths and 2x64 bit output paths • 32, or 64 bit shifting operations • 32 or 64 bit manipulation operations ENEL 619.23 -- Review of TigerSHARC Processor

19. Examples long int value = 128; long int high, low; low = value >> 2; high = value << 2; POSITIVE VALUE – LEFT SHIFT NEGATIVE VALUE – RIGHT SHIFT XR0 = 2;; XR1 = -XR2;; XR2 = 128;; //low = value >> 2; XR23 = ASHIFT XR2 BY –2;; Or XR23 = ASHIFT XR2 BY XR1;; //high = value << 2; XR22 = ASHIFT XR2 BY 2;; Or XR22 = ASHIFT XR2 BY XR0;; ENEL 619.23 -- Review of TigerSHARC Processor

20. TS101 ALU instructions • Under the RIGHT conditions can do multiple operations in a single instruction. • Instruction line has 4x32 bit instruction slots. • Can do 2 Compute and 2 memory operations. • This is actually 4 Compute operations counting both compute blocks. • One instruction per unit of a compute block, ie. ALU. • Since there are only 3 result buses, only one unit (ALU or Multiplier) can use 2 result buses. • Not all instructions can be used in parallel. ENEL 619.23 -- Review of TigerSHARC Processor

21. Dual Operation Examples • FRm = Rx + Ry, FRn = Rx – Ry;; • Note that uses 4(8) different registers and not 6(12) • The source registers used around the + and – must be the same. • Can be floating(single or extended precision) or fixed(32 or 64 bit) add/subtract. • FRm = MRa, MRa += Rx * Ry;; • MRa must be the same register(s) • Can be used on fixed(32 or 64 bit results), floating(32 or 40 bit results) and complex numbers. ENEL 619.23 -- Review of TigerSHARC Processor

22. Tackled today • Reference sources • Register file and operations • ALU operations • Multiplier operations • SHIFTER operations • Common errors • Example exercises ENEL 619.23 -- Review of TigerSHARC Processor