Logic Design CSCi 2021: Computer Architecture and Organization

Logic DesignCSCi 2021: Computer Architecture and Organization Chapter 4.2

Today • Hardware logic design concepts • RISC/CISC –if time • Y86 simulator if time

Last Time • Instruction Set Architecture • Similar state and instructions as IA32 • Simpler encodings • Somewhere between CISC and RISC • ISA tells you “what we can do” • Now we look at implementation or “how” • Skip a few slides

The Book • Read the book • Notice that we don’t talk about everything • Book isn’t perfect • Google works well to fill in the gaps

Overview of Logic Design • Fundamental Hardware Requirements • Communication: how to get values from one place to another • Computation: change values, produce new ones • Storage: remember values • Bits • Everything expressed in terms of values 0 and 1 • Communication • Low or high voltage on wire • Computation • Compute Boolean functions • Storage • Store bits of information

0 1 0 Voltage Time Digital Signals • Use voltage thresholds to extract discrete values from continuous signal • Simplest version: 1-bit signal • Either high range (1) or low range (0) • With guard range between them • Not strongly affected by noise or low quality circuit elements • Can make circuits simple, small, and fast

Computing with Logic Gates • Outputs are Boolean functions of inputs • Respond continuously to changes in inputs

Acyclic Network Primary Inputs Primary Outputs Combinational Circuits • Acyclic Network of Logic Gates • Continously responds to changes on primary inputs • Primary outputs become (after some delay) Boolean functions of primary inputs

Bit equal a eq b Bit Equality • Generate 1 if a and b are equal • Hardware Control Language (HCL) • Very simple hardware description language • Boolean operations have syntax similar to C logical operations • We’ll use it to describe control logic for processors HCL Expression booleq = (a&&b)||(!a&&!b)

b31 Bit equal eq31 a31 b30 Bit equal eq30 a30 Eq B = Eq b1 Bit equal eq1 A a1 b0 Bit equal eq0 a0 Word Equality Word-Level Representation • 32-bit word size • HCL representation • Equality operation • Generates Boolean value HCL Representation bool Eq = (A == B) uppercase

Bit-Level Multiplexor • Control signal s • Data signals a and b • Output a when s=1, b when s=0 s Bit MUX HCL Expression bool out = ? b out a

MUX • XOR

s b31 out31 a31 s b30 out30 MUX B Out a30 A b0 out0 a0 Word Multiplexor Word-Level Representation • Select input word A or B depending on control signal s • HCL representation • Case expression • Series of test : value pairs • Output value for first successful test HCL Representation int Out = [ s : A; 1 : B; ];

MIN3 C Min3 B A s1 s0 MUX4 D0 D1 Out4 D2 D3 HCL Word-Level Examples Minimum of 3 Words • Find minimum of three input words • HCL case expression • Final case guarantees match int Min3 = [ A < B && A < C : A; B < A && B < C : B; 1 : C; ]; 4-Way Multiplexor • Select one of 4 inputs based on two control bits • HCL case expression • Simplify tests by assuming sequential matching int Out4 = [ !s1&&!s0: D0; !s1 : D1; !s0 : D2; 1 : D3; ];

Hardware Control Language • Very simple hardware description language • Can only express limited aspects of hardware operation • Parts we want to explore and modify • Data Types • bool: Boolean • a, b, c, … • int: words • A, B, C, … • Does not specify word size---bytes, 32-bit words, … • Statements • bool a = bool-expr; • int A = int-expr;

HCL Operations • Classify by type of value returned • Boolean Expressions • Logic Operations • a && b, a || b, !a • Word Comparisons • A == B, A != B, A < B, A <= B, A >= B, A > B • Set Membership • A in { B, C, D } • Same as A == B || A == C || A == D • Word Expressions • Case expressions • [ a : A; b : B; c : C ] • Evaluate test expressions a, b, c, … in sequence • Return word expression A, B, C, … for first successful test

Hardware Control Language (HCL) • Abstract high-level language that defines circuit behavior • What could we do with such a language? • Simulate a circuit • Synthesize a circuit

2 1 0 3 Y Y Y Y A A A A X ^ Y X & Y X + Y X - Y X X X X B B B B OF OF OF OF ZF ZF ZF ZF CF CF CF CF A L U A L U A L U A L U Arithmetic Logic Unit • Combinational logic • Continuously responding to inputs • Control signal selects function computed • Corresponding to 4 arithmetic/logical operations in Y86 • Also computes values for condition codes

Instruction Code Function Code addlrA, rB sublrA, rB andlrA, rB xorlrA, rB 6 6 6 6 3 2 0 1 rA rA rA rA rB rB rB rB Mirrors Y86 ISA Add Subtract (rA from rB) And Exclusive-Or

Storage • Need a way to store information! Two types: • Hardware registers: single word • Random-access memory: multiple words • Clock determines when new values are loaded • clock delivers a periodic signal

Rising clock State = y y Output = y   Register Operation • Stores data bits • For most of time acts as barrier between input and output • As clock rises, loads input • Values propagate every clock cycle State = x x Input = y Output = x

valA Register file srcA A valW Read ports W dstW Write port valB srcB B Clock A Simple Random-Access Memory • Stores multiple words of memory • Address input (src, dst) specifies which word to read or write • Register file • Holds values of program registers • %eax, %esp, etc. • Register identifier serves as address • Multiple Ports • Can read and/or write multiple words in one cycle • Each has separate address and data input/output

Register file Register file y 2 valW valW W W dstW dstW x valA Register file srcA A 2 Clock Clock valB srcB B x 2 Rising clock y   2 Register File Timing • Reading • Like combinational logic • Output data generated based on input address • After some delay • Writing • Like register • Update only as clock rises 2 x

Summary • Computation • Performed by combinational logic • Computes Boolean functions • Continuously reacts to input changes • Storage • Registers • Hold single words • Loaded as clock rises • Random-access memories • Hold multiple words • Possible multiple read or write ports • Read word when address input changes • Write word as clock rises

CISC Instruction Sets: IA32 • Complex Instruction Set Computer • Dominant style through mid-80’s • Stack-oriented instruction set • Use stack to pass arguments, save program counter • Explicit push and pop instructions • Arithmetic instructions can access memory • addl %eax, 12(%ebx,%ecx,4) • requires memory read and write • Complex address calculation • Condition codes • Set as side effect of arithmetic and logical instructions • Philosophy • Add instructions to perform “typical” programming tasks

RISC Instruction Sets • Reduced Instruction Set Computer • Fewer, simpler instructions • Might take more to get given task done • Can execute them with small and fast hardware • Register-oriented instruction set • Many more (typically 32) registers – more h/w avail • Use for arguments, return pointer, temporaries • Only load and store instructions can access memory • Similar to Y86 mrmovland rmmovl • addl %eax, 12(%ebx,%ecx,4) => ??? • No Condition codes • Test instructions return 0/1 in register

CISC vs. RISC • Original Debate • Strong opinions! • CISC proponents---easy for compiler, fewer code bytes • RISC proponents---better for optimizing compilers, can make run fast with simple chip design • Current Status • For desktop processors, choice of ISA not a technical issue • With enough hardware, can make anything run fast • Code compatibility more important • For embedded processors, RISC makes sense • Smaller, cheaper, less power

Find length of an array/list Write with pointer code Compile with gcc -O2 -S Result (inside len2) ecx -> len edx -> a eax -> *a Y86 Code Generation Example L24: movl (%edx),%eax incl %ecx L26: addl $4,%edx testl %eax,%eax jne L24 /* Find number of elements in null-terminated list */ int len2(int a[]) { intlen = 0; while (*a++) // ? a[len++] len++; return len; }

Simulating Y86 Program • unix> yis/ssimeg.yo • Instruction set simulator • Computes effect of each instruction on processor state • Prints changes in state from original • Stopped in 41 steps at PC = 0x16. Exception 'HLT', CC Z=1 S=0 O=0 • Changes to registers: • %eax: 0x00000000 0x00000003 • %ecx: 0x00000000 0x00000003 • %edx: 0x00000000 0x00000028 • %esp: 0x00000000 0x000000fc • %ebp: 0x00000000 0x00000100 • %esi: 0x00000000 0x00000004 • Changes to memory: • 0x00f4: 0x00000000 0x00000100 • 0x00f8: 0x00000000 0x00000015 • 0x00fc: 0x00000000 0x00000018

Next Time • Sequential CPU implementation • Read Chapter 4.3 • Have a GREAT Spring Break!

Logic Design CSCi 2021: Computer Architecture and Organization