1 / 22

On Reliable Modular Testing with Vulnerable Test Access Mechanisms

On Reliable Modular Testing with Vulnerable Test Access Mechanisms. Lin Huang, Feng Yuan and Qiang Xu. Purpose. Is on-chip data transmission reliable? What is the solution? Correction Retransmission Hybrid schemes They are helpful in normal functional mode

natala
Download Presentation

On Reliable Modular Testing with Vulnerable Test Access Mechanisms

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. On Reliable Modular Testing with Vulnerable Test Access Mechanisms Lin Huang, Feng Yuan and Qiang Xu

  2. Purpose • Is on-chip data transmission reliable? • What is the solution? • Correction • Retransmission • Hybrid schemes • They are helpful in normal functional mode • However, how about modular testing? Cross talk Yield loss IR drop Yield loss and even alpha particle hits …

  3. Agenda • Introduction to Modular Testing • Test Data Transmission “Error-Free” Assumption • Impact of Fault-Tolerant Schemes • The Proposed Solution • “Jitter-Aware” Test Wrapper Design • “Jitter-Transparent” ATE Interface Design • Experimental Results • Conclusion

  4. Introduction to Modular Testing • “Divide and conquer” manner • test wrapper • test access mechanisms (TAMs) • ATE Interface basic • TAM designs classification • dedicated bus-based access scheme • functional access scheme

  5. Reuse On-Chip Network as TAM

  6. “Error-Free” Assumption is Questionable • Existing work assumes test data transmission to be error-free • It is questionable when at-speed functional interconnects are reused as TAMs

  7. Fault Tolerance Schemes • Retransmission and hybrid schemes are mainstream techniques to achieve fault-tolerant communication • Retransmission brings problems • Test traffic jitter • Test bandwidth mismatch

  8. The Impact of Retransmission Scheme

  9. The Significance of These Problems • Given the number of flits in the entire test data volume , the flit error rate , the potential yield loss can be expressed as • When and flit size is 32 bits, the test yield loss for the chip containing 21.5M gates [1] is 11.47% ! [1] C. Barnhart et al, Extending OPMISR Beyond 10x Scan Test Efficiency. IEEE Design & Test of Computers, 19(5):65-73, Sep.-Oct. 2002

  10. Buffer-Only Solution • Given the flit injection rate is 0.1 flits per cycleand the extra delay caused by one retransmission is 40 cycles st nd The 1 The 2 retransmission retransmission Shortage of reserved flits 5 reserved flits 1 reserved flits

  11. “Jitter-Aware” Test Wrapper Design • Two extra states: • HALTIN • HALTOUT Input HALT IN Blocked SHIFT CAPTRUE Output Blocked HALT OUT IEEE 1500 Finite State Machine

  12. Wrapper Architecture

  13. Wrapper Input Control Kernel Control IPath _ Blocked MCmd _ I n SCmdAccept _ I n S can _ E n IBMU _ Ctrl Block _ Ctrl Output Control SCmdAccept _ O ut Gated _ Clk MCmd _ O ut OPath _ Blocked OBMU _ Ctrl S can _ Clk OCP _ Clk Control Logic Clock Division Control Logic of Test Wrapper

  14. “Jitter-Transparent” ATE Interface • If the ATE operate in a stream mode … • Minimum buffer size: that is able to tolerate the extra delay caused by one retransmission • Given the flit error rate and the number of flits , the test yield loss can be computed as follows: Without Buffer:

  15. “Jitter-Transparent” ATE Interface • We propose to divide the entire input test data flow into segments and insert a small section of “don’t-care” bits Data transmission direction

  16. Test Yield Improvement • Given the flit error rate , the number of flits , and the number of segments , the test yield loss can be computed as follows: Without Buffer: With Minimum Buffer Size:

  17. Experimental Setup • Commercial 90nm CMOS technology • Area overhead • 838 two-input NAND equivalent gates • An industrial circuit[2] • Number of gates: 2.6M • Number of scan cells: 274K • Compressed scan test data volume: 106M • System parameters • Flit injection rate: 0.25 flit per cycle • Flit size: 32 bits • Retransmission delay: 40 cycles [2] C. Barnhart et al, OPMISR: The Foundation for Compressed ATPG Vectors. In Proc. IEEE International Test Conference, pp. 748-757, Nov. 2001

  18. Yield Loss: 0.05% Yield Loss: 4.41% Test Yield Loss for a Core with 2.6M Gates Flit Error Rate: 10-7 Yield Loss: 28.20% Cost: Testing Time Penalty: 0.15%

  19. Proposed Technique vs. Buffer-Only Solution nb: Buffer size for buffer-only solution λ: Flit error rate np: Buffer size for the proposed design ΔTp: Testing time extension ratio of the proposed design

  20. Conclusion • The “error-free” assumption of existing work is questionable • Fault-tolerant schemes may lead to traffic jitter and variable test bandwidth • We propose a “jitter-aware” test wrapper and an on-chip “jitter-transparent” ATE interface to achieve reliable modular testing • Experimental results demonstrate the effectiveness

  21. Thank you !

  22. Timing Diagram of Test Wrapper

More Related