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Noise Canceling in 1-D Data: Presentation #3

Feb 2 nd , 2005 Size Estimates and Floorplan. Noise Canceling in 1-D Data: Presentation #3. Seri Rahayu Abd Rauf Fatima Boujarwah Juan Chen Liyana Mohd Sharipp Arti Thumar. M2. Project Manager: Bobby Colyer. Overall Project Objective:

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Noise Canceling in 1-D Data: Presentation #3

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  1. Feb 2nd, 2005 Size Estimates and Floorplan Noise Canceling in 1-D Data: Presentation #3 Seri Rahayu Abd Rauf Fatima Boujarwah Juan Chen Liyana Mohd Sharipp Arti Thumar M2 Project Manager: Bobby Colyer Overall Project Objective: Implementing Noise Cancellation Algorithm in Hardware

  2. Status • Design proposal (Done) • Architecture proposal (Done) • Behavioral Verilog simulation and test bench (Done) • Size Estimates and Floorplan: • Structural Verilog (85%) • Revised transistor count (Done) • Floorplan (Done) • To be done: • Schematics (15%) • Layout (5%) • Spice simulation

  3. Last week’s Block Diagram…

  4. Revised Block Diagram

  5. Behavioral Simulation Output Original C Code Simulation Results: Input: 9.325461 Output: 9.650836 Error: -0.325 Converted Values from Verilog Simulation: Input: 9.3125 Output: 9.8227359 Error: -0.5 **Difference in values due to 16-bit precision

  6. Results Comparisons (Output)

  7. Result Comparison (Error)

  8. Structural Verilog Example: Floating Point Multiplier

  9. Metal Directionality Note: Depending on the complexity of the blocks, metal 1 and metal 2 may be used in both directions.

  10. Local vs Global Interconnects Note: Vdd! & Ground: M1, M2 Internal Routing: M1, M2 Clock & Reset: M3, M4 Global Routing: M3, M4

  11. Last week’s transistor count…

  12. A more accurate transistor count…

  13. Tentative Floorplan Total Area: ~190,000 µ²

  14. Area Estimates

  15. Ratio/Density • Aspect Ratio: • 415µ x 450µ = 1:1.08 • Block Porosity: • 22000 transistors/190000µ2 • 0.12 transistors/µ2

  16. Last week’s challenges… • Timing issues • Need to reuse hardware (multipliers) (reduced from 5 to 3) • Clock skew (needs to be addressed) • Pipelined architecture to increase speed and throughput (not needed) • SRAM implementation (not needed) • ROM implementation (completed) • Transistor count is too high (reduced through hardware reuse and block optimization)

  17. This week’s challenges… • Still working on finalizing out designs for the floating point adders and multipliers • Wallace tree multiplier vs Array multiplier • Wallace implementation is smaller because it reuses the intermediate products of the individual bits • Leading zero counter for normalizing block

  18. Questions?

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