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Improvements to the Bose Noise Canceling Headphones

Improvements to the Bose Noise Canceling Headphones. Nathan Hanagami. Project Outline. Research available DSP and A/D Converter Units Implement DSP version of Corrected Compensation Curve Add features (Variable EQ/Reverb settings) Use spar processing power to assist in Noise Cancellation

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Improvements to the Bose Noise Canceling Headphones

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  1. Improvements to the Bose Noise Canceling Headphones Nathan Hanagami

  2. Project Outline • Research available DSP and A/D Converter Units • Implement DSP version of Corrected Compensation Curve • Add features (Variable EQ/Reverb settings) • Use spar processing power to assist in Noise Cancellation • Convert Digital portions to FPGA design • Optimizations and Work on ASIC layout

  3. Develop DSP • Possible Suppliers • Analog Devices • TI • Xylinx • Linear Tech. • Wolfson Microelectronics • National • Etc.

  4. Considerations • Sampling Rate (Minimum 44.1 kHz) • Sampling Width (Minimum 18 bit) • Propagation Delay • Power Consumption • Physical Size • Not as concerned about fitting on existing DSP

  5. Alternatives to Fitting on Chip • Integrate EQ controller into cable for extra circuitry • Design as upgrade that existing headphones can be plugged into (requires slightly different design than fully replaceable unit) To Headphones From Stereo DSP

  6. EQ/Reverb Upgrade • Allow user to set EQ based on Genre of Music (Rock, Pop, Jazz, Orchestral, etc.) • Allow user to set Reverb to various environments (Concert Hall, Small room, Jazz Hall, etc.) • Based on assumption that ideal frequency response varies depending on type of music.

  7. Assist in Noise Cancellation • Based on meeting propagation delay requirements. Alternatively will layout hypothetical design parameters • Work either in series to further attenuation • In parallel to increase cancellation bandwidth

  8. Convert to FPGA design • Adds Customization allowing for easier production • Code in VHDL or Verilog • Designed to Replace Functionality of DSP, A/D remain non-integrated

  9. Design Layout for ASIC • Costs will probably prevent actual custom chip fabrication • Work on Layout Design • Present a hypothetical model

  10. Optimization • Reduce Power Consumption • Minimize chip area/work on layout • Eliminate unneeded parts and minimize costs • Work on possible improvements to analog amplification system

  11. Project Layout

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