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Data Management Challenges of CPU Design

Kiron Pai Intel Corporation. Data Management Challenges of CPU Design. Feb 25, 2010 EDP 2010. Agenda. Introduction Problem Scope Silicon Stepping Methodology Requirements Reduce, Reuse and Recycle Workflows Conclusion What did we accomplish? Q&A. Introduction. Problem Scope.

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Data Management Challenges of CPU Design

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  1. Kiron PaiIntel Corporation Data Management Challenges of CPU Design Feb 25, 2010 EDP 2010

  2. Agenda • Introduction • Problem Scope • Silicon Stepping Methodology • Requirements • Reduce, Reuse and Recycle • Workflows • Conclusion • What did we accomplish? • Q&A

  3. Introduction

  4. Problem Scope • Multiple silicon steppings and incremental improvements • Design Cost and Performance • Multiple product configurations and design reuse • Time to Market for multiple customer segments • Concurrent development of different product configurations • Design Productivity • Flexibility: adapt to changing requirements • Market needs move during design and production cycle

  5. Past Project – A look back • Started as a 1 product configuration • By the end, there were 4 different product configurations for 3 different market segments • Challenges included • Efficient design reuse across • Product configurations • Steppings • Multi-geo development sites: a fact of life now… Need to understand and prevent Chaos

  6. Past Project - Design Inheritance Product Independent Product Specific A B D C Product 1 G H I A C Product 2 Product 3 A B A Product 4

  7. Past Project - Stepping Methodology • Data inheritance from reference steppings • Product independent v/s product specific inheritance • Inheritance maintained using links • Edits enabled by making copies Reused design data that didn’t change across steppings and product configurations Multiple sites maintained using edit access controls and nightly synch ups Reigned in Chaos to bring Stability

  8. Current Project - Requirements • Support for • Concurrent development • Reuse of data across steppings • Multi sites, multi steppings, multi products • Reuse at the smallest manageable granularity

  9. Current Project - The Philosophy Inherited from A0 BlockABlockB Branched to BlockA B0 BlockB BlockA BlockB C0 BlockA D0 BlockB Leverage reference project as long as possible

  10. A0 Workflow Populate fub • Central team: Populate data into A0 libs • Central Team: Unlock libs for edit • Design Team: Enabled to checkout, checkin • Design Leads: Lock fub down in preparation of closure leading to lockdown Unlock fub Edit, Verify, Review Lock fub FUB = Functional Unit Block, anywhere from 10K to 500K devices

  11. Minor edits Stepping Workflow Unlock Fub • Integration team: Unlock fub for edits • Design Team: Enabled to checkout, checkin • Integration Team: Lock down fub Edit, Verify, Review Lock Fub

  12. New Stepping Workflow Branch Fub First ECO • Design Leads: For first ECO in new stepping, branch databases and unlock for edits • Design Leads: Unlock block for future edits for blocks that have been previously branched, edited and locked. • Design Team: Enabled to checkout, checkin • Design Leads: Lock blocks down in preparation of closure leading to lockdown Unlock Fub Future ECO’s Edit, Verify, Review Lock Fub

  13. Conclusion

  14. Recent Project - Design Inheritance Product Independent Product Dependent External IP B C A A J K L Product 1 B D E A Product 2 B C

  15. Recent Project – Reuse across steppings

  16. Q&A

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