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Lecture 15: DRAM Design

Lecture 15: DRAM Design. Today: DRAM basics, DRAM innovations (Section 5.3). DRAM Main Memory. Main memory is stored in DRAM cells that have much higher storage density DRAM cells lose their state over time – must be refreshed periodically, hence the name Dynamic

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Lecture 15: DRAM Design

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  1. Lecture 15: DRAM Design • Today: DRAM basics, DRAM innovations • (Section 5.3)

  2. DRAM Main Memory • Main memory is stored in DRAM cells that have much • higher storage density • DRAM cells lose their state over time – must be refreshed • periodically, hence the name Dynamic • DRAM access suffers from long access time and high • energy overhead • Since the pins on a processor chip are expected to not • increase much, we will hit a memory bandwidth wall

  3. … DRAM Organization Array 1/8th of the row buffer One word of data output DRAM chip or device DIMM Rank Bank Memory bus or channel On-chip Memory Controller 3

  4. DRAM Array Access 16Mb DRAM array = 4096 x 4096 array of bits 12 row address bits arrive first Row Access Strobe (RAS) 4096 bits are read out Eight bits returned to CPU, one per cycle 12 column address bits arrive next Column decoder Column Access Strobe (CAS) Row Buffer

  5. Salient Points I • DIMM, rank, bank, array  form a hierarchy in the • storage organization • Because of electrical constraints, only a few DIMMs can • be attached to a bus • Ranks help increase the capacity on a DIMM • Multiple DRAM chips are used for every access to • improve data transfer bandwidth • Multiple banks are provided so we can be simultaneously • working on different requests

  6. Salient Points II • To maximize density, arrays within a bank are made large •  rows are wide  row buffers are wide (8KB read for a • 64B request) • Each array provides a single bit to the output pin in a • cycle (for high density and because there are few pins) • DRAM chips are described as xN, where N refers to the • number of output pins; one rank may be composed of • eight x8 DRAM chips (the data bus is 64 bits) • The memory controller schedules memory accesses to • maximize row buffer hit rates and bank/rank parallelism

  7. Salient Points III • Banks and ranks offer memory parallelism • Row buffers act as a cache within DRAM • Row buffer hit: ~20 ns access time (must only move • data from row buffer to pins) • Empty row buffer access: ~40 ns (must first read • arrays, then move data from row buffer to pins) • Row buffer conflict: ~60 ns (must first writeback the • existing row, then read new row, then move data to pins) • In addition, must wait in the queue (tens of nano-seconds) • and incur address/cmd/data transfer delays (~10 ns)

  8. Technology Trends • Improvements in technology (smaller devices)  DRAM • capacities double every two years, but latency does not • change much • Power wall: 25-40% of datacenter power can be • attributed to the DRAM system • Will soon hit a density wall; may have to be replaced by • other technologies (phase change memory, STT-RAM) • Interconnects may have to be photonic to overcome the • bandwidth limitation imposed by pins on the chip

  9. Latency and Power Wall • Latency and power can be both improved by employing • smaller arrays; incurs a penalty in density and cost • Latency and power can be both improved by increasing • the row buffer hit rate; requires intelligent mapping of • data to rows, clever scheduling of requests, etc. • Power can be reduced by minimizing overfetch – either • read fewer chips or read parts of a row; incur penalties • in area or bandwidth

  10. Density Wall • New emerging non-volatile memories that have better • scalability; instead of storing data in the form of charge, • data encoded in cell resistance (phase change memory) • or in electron spin (spin torque transfer STT-RAM) • Phase change memory: the cell can be either amorphous • (high resistance, represents zero) or crystalline • (low resistance, represents one) • Data is written by heating the material and cooling it at • different rates (with electrical pulses); short intense • pulse  amorphous; long medium pulse  crystalline

  11. Phase Change Memory • Can also have multi-level cells; each resistance value • represents a different encoding; enables scalability • Each cell can only be written about 10 times; need • many tricks to improve endurance: write on change, • shift bits within a row, re-map data to rows, etc. • Reads are relatively quick (~50 ns), writes are very slow • (~1000 ns) • Has potential to replace DRAM, disk, or both in at least • some classes of computers 8

  12. Photonics • A single waveguide carries light that was generated • off-chip to multiple “nodes” • The nodes can act as transmitters or receivers; • transmitters can vary the amplitude of a light signal • based on the input electrical signal • Since multiple light wavelengths can be multiplexed on • a waveguide and because each wavelength can carry a • different signal, photonic interconnects have high bandwidth • The EO and OE conversion overhead means that the • photonic signal must travel far enough to out-do an • electrical interconnect in terms of latency and power

  13. Title • Bullet

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