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ICU Requirements and Interfaces Renato Orfei Riccardo Cerulli Anna Maria Di Giorgio

HIFI Critical Design Review. ICU Requirements and Interfaces Renato Orfei Riccardo Cerulli Anna Maria Di Giorgio Sergio Molinari Scige’ John Liu’ IFSI-CNR. Performance Drivers of the ICU Design. Contract specifications had to be ready by the end of October 1999.

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ICU Requirements and Interfaces Renato Orfei Riccardo Cerulli Anna Maria Di Giorgio

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  1. HIFI Critical Design Review ICU Requirements and Interfaces Renato Orfei Riccardo Cerulli Anna Maria Di Giorgio Sergio Molinari Scige’ John Liu’ IFSI-CNR

  2. Performance Drivers of the ICU Design Contract specifications had to be ready by the end of October 1999 • Boards design and manufacturing through contract (CGS) (3 DPU/ICU: 71 boards!!) • Electronic design to be frozen early (mainly the Interfaces with S/C and SSs) • CPU: powerful enough to handle 100kBit/s Bit Rate (ADSP21020, 20 MHz clock) • Interfaces: capable of managing 1 Mbit/s data gathering (10 times the Bit Rate) • Data Memory and Program Memory: maximum possible with the CGS design • HW I/F to/from SSs: Balanced lines drivers and receivers • HW I/F to/from S/C: MIL-STD-1553B, transformer coupled • Quality level of components SCC-B through CPP • Units: AVM, EQM, FM, spare boards for FS.

  3. Functional Requirements • Interface with S/C telemetry/telecommand subsystem and power system in order to: • collect, format and transmit data to the S/C • accept, analyse and execute telecommands • convert the 28 V line to suitable voltages for ICU and FCU. • Interface with SUBSYSTEMS in order to: • set the current observing mode • upload SW • acquire science data and HK • Manages the observing modes and autonomy functions.

  4. Requirement ID Description Reference ICU-FUN-01 The interfaces of the ICU with the subsystems shall be designed in order to comply with the maximum output data rates of the WBS-v-h AD5 sect. 4.4 ICU-FUN-02 The interfaces of the ICU with the subsystems shall be designed in order to comply with the maximum output data rates of the HRS-v-h AD5 sect. 4.4 ICU-FUN-03 The interfaces of the ICU with the subsystems shall be designed in order to comply with the commanding of all mechanisms. AD5 sect. 4.4 ICU-FUN-04 The interfaces of the ICU with the subsystems shall be designed in order to comply with the setting of all variable parameters. AD5 sect. 4.4 Performance Requirements NOTE: AD5 is HIFI ICD; AD2 is IID-A; AD3 is IID-B

  5. ICU-FUN-05 The ICU shall be able to handle the adopted standard MIL-STD-1553B for the interface with the spacecraft Packet telemetry and a telemetry rate of 100 kbps. AD2 sect. 5.11.6 ICU-FUN-06 The ICU shall be able to handle the adopted standard MIL-STD-1553B for the interface with the spacecraft Packet telemetry and provide a HK packet at least once per second. AD2 sect. 5.11.6 ICU-FUN-07 The ICU shall be able to handle the adopted standard MIL-STD-1553B for the interface with the spacecraft Packet telecommand and a command rate of 4 kbps. AD2 sect. 5.11.6 ICU-FUN-08 maximum power consumption of ICU 42.6 W AD5 sect. 4.3.1.1 ICU-FUN-09 Maximum power drain of the ICU itself 22.3 W AD5 sect. 4.3.1.1 ICU-FUN-10 max power (including DC/DC converter efficiency) to the FCU: 20.3 W AD5 sect. 4.3.1.1 ICU-FUN-11 The maximum allocated mass is 7 kg AD3 sect. 5.5 Technical Requirements

  6. Requirement ID Description Reference ICU-SAF-01 Failure of the ICU, or one of its components, shall not affect the interface with the satellite. IFSI ICU- SAF -02 Failure of any component in the ICU shall not damage any redundant or backup component designed to replace that component in the subsystem IFSI ICU- SAF -03 It shall be possible to break via software all electronic control loops. IFSI ICU- SAF -04 The ICU shall monitor the operational status of the instrument and take appropriate pre-defined actions in case of error. IFSI Operational Safety

  7. Requirement ID Description Reference ICU-OPE-01 The ICU shall be designed for an overall lifetime of 10 years, with 3.5 years in orbit. IFSI Lifetime

  8. Requirement ID Description Reference CPU board design ICU-DES-01 The CPU board shall be based on the DSP TEMIC TSC21020, at least 20 MHz clock, chip. IFSI ICU-DES-02 The CPU board shall carry a watch-dog system that can be enabled/disabled through a jumper. IFSI ICU-DES-03 The CPU board shall include a programmable timer, with a precision of 1 s and a max capacity of 100s. IFSI ICU-DES-04 The CPU board shall have no more than one bit error per year. IFSI ICU-DES-05 The CPU board shall have at least 32 kbytes of PROM memory with the bootstrap programme and software to face emergency situations and for maintenance. IFSI Design Requirements (1/5)

  9. ICU-DES-06 The CPU board shall have at least 1 Mbytes of EEPROM memory for the main programme. IFSI ICU-DES-07 The CPU board should have at least 512 Kword (48 bit word) of PROGRAMME static RAM. IFSI ICU-DES-08 The CPU board should have at least 512 Kword (32 bit word) of DATA static RAM. IFSI ICU-DES-09 It shall be possible to modify the EEPROMs content during flight through a maintenance programme and through a software programme coming from the telecommand system. IFSI ICU-DES-10 The CPU board shall carry on PROM the following basic software: -a driver for the interface circuit with the S/C; -a programme loader through the telemetry; -a function to carry-out the EEPROMs checksum test. Moreover the CPU board shall support the EONIC Virtuoso operating system . IFSI ICU-DES-11 The frequencies generated within the ICU shall come as far as possible from the same oscillator, in order to limit the EMC problems. IFSI Design Requirements (2/5)

  10. Low speed interface design ICU-DES-12 All links use balanced line drivers and receivers. AD5 sect. 4.4.1 ICU-DES-13 All data transactions with the addressed subsystem (addr. In TX_DAT), are initiated by ICU. ICU shall send data to all subsystems using one serial data line TX_DAT (see figure 2.6) and can send both commands and HK requests via this line. AD5 sect. 4.4.1 ICU-DES-14 ICU shall be able to accept the subsystems responses via the RX_DAT line (see figure 2.6). AD5 sect. 4.4.2 ICU-DES-15 The Clock rate will be 312.5 kHz. AD5 sect. 4.4 ICU-DES-16 Clock and TX_DAT shall be generated by ICU and distributed to all subsystems. AD5 sect. 4.4 ICU-DES-17 RX_DAT lines, coming from FCU, LCU and LSU subsystems, shall be multiplexed in the ICU. AD5 sect. 4.4 ICU-DES-18 For internal reading of analogue signals an A/D converter (12 bit) plus MPX (8 Channels) shall be provided in order to digitise the information of an internally conditioned thermistor and of the ICU DC/DC converter voltages. IFSI Design Requirements (3/5)

  11. High speed interface design ICU-DES-19 All links use balanced line drivers and receivers. AD5 sect. 4.4.3 ICU-DES-20 Four synchronous serial input interfaces shall be provided, each of which with 8 KW 24 Bit FIFO. The clock, gate and data signals are coming from the subsystems. All data shall be received by the ICU at the same time. The clock speed is 250 kHz for WBS-v-h and 2.5 MHz for HRS-v-h. AD5 sect. 4.4.3 Design Requirements (4/5)

  12. DC/DC Converter design ICU-DES-21 The DC/DC converter board shall have the following main characteristics: -input DC voltage ranging from 26 to 30 V AD2 sect. 5.9.5.2 ICU-DES-22 - efficiency of 70% or better; IFSI ICU-DES-23 - input filter with EMI-EMC properties (following ESA EMC/EMI specs); AD2 sect. 9.5.6 ICU-DES-24 - overall characteristics in agreement with Herschel IID-A (inrush current etc.); AD2 sect. 5.9.5.1 Design Requirements (5/5)

  13. Mass Budget • Components of the mass breakdown (weights inferred from the AVM values):BOX (240x258x194 mm^3, Anticorodal 6082; 2.7 g/cm^3): Baseplate 1071 g Front wall: 230 g Front wall connectors (delta:E) 150 g Bak wall: 230 g Lateral walls (2 of): 988 g Cover: 368 g Total Box weight: 3037 g • CPU boards (2 of): 960 g • P/L I/F Boards (2 of): 640 g • DC/DC boards (2 of): 1580 g • Motherboard: 520 gTotal Boards weight 3700 g • Screws etc. (E): 100 g • Cabling (E): 300 g • Conformal Coating (60g/Board, E) 420 gTotal Other weights 820 g Total estimated weight: 7557 g (+ - 200 g)

  14. CPU Board Power Budget [Watt] Item +5V & 2.5V +15V -15V Duty cycle % Power Supply Nominal Peak Nominal Peak Nominal Peak Nominal Nominal DSP 1,5 2 0 0 0 0 100 1,5 DPR 2 3,2 0 0 0 0 10 0,2 TSS901 0,6 1 0 0 0 0 10 0,06 SRAM @1MHz 6 6 0 0 0 0 80 4,8 EEPROM 0,1 0,5 0 0 0 0 100 0,1 Glue logic 1 1 0 0 0 0 80 0,8 FPGA 0,125 0,25 0 0 0 0 100 0,125 Total 11,32 13,95 0 0 0 0 7,58 Power Budget

  15. PL I/F Board [Watt] Item +5V +15V -15V Duty cycle % Power Supply Nomin. Peak Nomin. Peak Nomin. Peak Nomin. Nomin. BU61582 0,7 1,2 3,45 3,825 100 4,15 FIFO 0,09 9,9 100 0,09 RS422 Receiv. 0,3 0,4 80 0,24 RS422 Transm. 0,9 1 80 0,72 Analogue Section 0,15 0,2 0,111 0,181 0,33 0,535 40 0,23 Glue logic DC 1 1 80 0,8 Glue logic AC 0,4 0,6 80 0,32 FPGA 0,125 0,25 100 0,125 3,66 18,15 0,111 0,181 3,78 4,36 6,67

  16. Power1 (W) Power2 (W) Total (W) HIFI ICU 14.2 20.3 25.4 HIFI FCU 23.8 34 42.5 ICU Total Power Budget Power1 : the power drained on the secondary power lines. Power2: the power drained on the primary power lines (+ - 28 V) including a DC/DC converter efficiency of 70%. Total: The total power including a contingency of 25%.

  17. ICU BOX InterfaceControl Drawing

  18. ICU BOX TOP VIEW

  19. JTAG DSP 21020 RAM 1355 (Mounted only for PACS) MEZZANINE FPGA EPROM 20 MHz CPUBOARD

  20. FIFOs FIFOs S/S I/Fs A/D Conv. 16 MHz 1553B (S/C I/F) Long Stub Trafos “A” and “B” FPGA I/F BOARD

  21. AVM Box at Utrecht (during preliminary integration tests) JTAG PROBE CPU BOARD I/F BOARD DC/DC BOARD

  22. ICU Block Diagram & Memory Organisation 4 S/S High Speed Serial I/F Data RAM 512 Kw2 MB Data area32 bit words 262 Kw1 MB EEPROM Inst. Program 4 S/S Low Speed Serial I/F DPU TSC 21020 DSP PROM Kernel Telemetry upload SW 5.4 Kw 32 KB FPGA State Machine 2 S/S Low Speed Serial I/F Bus Program area48 bit words Program RAM Loaded from EEPROM S/C I/F PWR TC/TM 512 Kw3 MB

  23. CDMS COMMUNICATION I/F

  24. MIL-STD-1553B interface 8 Kword dual port memory 1 INT per frame (64 per sec)

  25. Subsystems Interfaces All HW interfaces implemented with balanced drivers and receivers (26C31 and 26C32) • 4 high speed serial unidirectional links for science data and HK collection: - 2 links from WBSv-h to ICU- 2 links from HRSv-h to ICU • 4 low speed serial bus mono-directional links to Command WBSv-h and HRSv-h • 2 low speed serial bus bi-directional links to LCU and FCU • The links will be used for subsystems commanding and reception of housekeeping parameters in the case of LCU and FCU and only for commanding for WBSv-h and HRSv-h

  26. High Speed Interface • 2.5 MHz (HRS) & 250 kHz (WBS) clocks • 24 bit data words • 8 Kw FIFO FIFO half full to INT

  27. Low speed interface All data transactions with the addressed subsystem (addr. In TX_DAT), are initiated by ICU.ICU will send data to all subsystems using one serial data line TX_DAT and can send both commands and HK requests via this line. Subsystems, when requested by the ICU, will send responses via RX_DAT line. A command is made of 2 start bit, 4 address bit and 26 data bit.HK request is made of 2 start bit and 4 address bit and 10 other selection address bit. After transmission of these 16 bit, the TX_DAT line shall stay high (max 625 clock cycles) until the corresponding HK response has been received, otherwise a time-out will reset the TX_DAT and a flag will be issued. Then 1 stop bit will follow.A HK response shall consist of 2 start bit, 4 address bit, 10 other selection address bit and 16 data bit. The figure shows the HW protocol. Clock rate 312.5 KHz

  28. Low Speed InterfaceCircuit Scheme No buffer Wait for response

  29. Interrupt generation Half Full FIFO # 1 Irq 0 Half Full FIFO # 2 Interrupt Manager Half Full FIFO # 3 Irq 1 (NC) Half Full FIFO # 4 Interrupt Priority DSP Irq 2 1553 SC I/F TC - TM Irq 3 Timer(32 bit) 1 MHz clk High

  30. CDMS COMMUNICATION I/F Buffers • Hardware: 2 MB of DATA Memory • Assumption: 1 MB used for CDMS I/F buffer TC rate ~ 0.5 kBps 128 kB TC buffer CDMS TM rate ~ 12 kBps 872 kB TM buffer Half of the baseline data memory is used to buffer TC (256 s) and TM (72 s) at 100 kbps data rates. • TC buffer length ~ 256 sec • TM buffer length ~ 72 sec

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