Proposal Presentation Vishal Gupta 20th September, 2005

1. Proposal Presentation Vishal Gupta 20th September, 2005 An Accurate, Trimless, High PSRR, Low-Voltage, CMOS Reference IC

2. Outline • Introduction • Motivation • State-of-the-Art • Proposed System • Contributions and Future Work

3. Voltage References • Establish a stable, reliable voltage that the rest of the circuits in an IC can use • Uses of a voltage reference • Establish standard unit (A/D) • Build stable supply (regulator) • Set up bias point (op amp) • Most important specification: ACCURACY across variations temperature, process, voltage, noise Introduction

4. Bandgap References • In IC – bandgap references popular • VBE is Complementary-to-Absolute-Temperature • ΔVBE is Proportional-to-Absolute-Temperature • VREF ≈ 1.2V ( ≈ Eg of Si) • Sub-bandgap references also possible Introduction

5. Concept of System Introduction

6. Motivation • Rising market for portable applications like cellular phones, PDAs, digital cameras • Primary market demands • Low cost (yet maximum performance) • High functionality (audio, video, web) • Small form-factor

7. Low Cost and High Performance • Figure-of-merit for a reference – ACCURACY! • Current practice – improve accuracy through trimming • Increase test times • Increase die area • Increase pin count • Increase cost • Need trimless Motivation

8. High Functionality Motivation

9. High Functionality • Requirements of reference • High Power Supply Ripple Rejection: to provide quiet power supply • Regulated output: to enhance immunity to noise and supply transients • Sub-bandgap output voltage: to operate in low-voltage conditions • Low power operation: to have minimal impact on system efficiency Motivation

10. Motivation

11. State-of-the-Art • Low-voltage, low power, regulated, integrated CMOS references • Improving accuracy (and reducing required trim range) • Improving PSRR performance and noise immunity

12. CMOS Voltage References Both topologies CMOS, low power, integrated A B State-of-the-Art Regulated, Low Zout Not sub-bandgap! Sub-bandgap Not regulated, High Zout!

13. Improving Accuracy – A Study of Process-Induced Errors State-of-the-Art

14. Improving Accuracy – Reducing Offset through DEM Switching schemes - dynamic element matching (DEM), chopper stabilization, and auto-zeroing - are often used to eliminate the offset of op amps. State-of-the-Art These schemes are noisy and limit system bandwidth.

15. Improving Accuracy – A Study of Package Shift Shift in the reference voltage that occurs due to packaging. die plastic package at 175°C State-of-the-Art at 25°C Random: Filler in plastic packages produces randomly distributed vertical stress on die. Systematic: Difference in thermal coefficient of expansion of package and silicon causes strain on die as system cools from molding temperature.

16. Improving Accuracy – Reducing Package Shift State-of-the-Art

17. Improving PSRR Performance – An Analysis of PSRR • Power Supply Ripple Rejection (PSRR) studied in: • Operational Amplifiers • Linear Regulators State-of-the-Art PSRR closely related to open loop parameters.

18. Improving PSRR Performance • Low efficiency, large dropout • High system complexity, high noise State-of-the-Art

19. Motivation Reviewed

20. Proposed System • Bandgap reference is all-CMOS, regulated, and low-voltage (sub-bandgap) • Survivor scheme improves accuracy without adding noise or cost • High PSRR strategy is simple, effective, and quiet

21. Bandgap Reference – Concept • Voltage mode approach • OA1 offset is systematic and PTAT • Diode D provides CTAT voltage • Op amp OA1 and MPO provide high loop gain • Output regulated Proposed System

22. Bandgap Reference – Schematic Proposed System

23. Bandgap Reference – LPNP Devices Proposed System • 10 samples of lateral PNP devices characterized over 2 runs: • BF = 100 A/A • VAF = 6 V • IS = 70E-18 A

24. Bandgap Reference – Simulation Results Proposed System

25. Survivor – Concept Reduces offset by choosing best matched pairs to implement analog block from number of similar pairs at startup. • Bank of device pairs fabricated. • Two pairs compared for mismatch in comparator cell. • Digital engine discards loser pair and provides replacement. • Survivor emerges after final comparison. Proposed System

26. Survivor – Comparator • S1 switches pair MN21-22 to change polarity of VOS2. • Latch stores result of previous comparison. • XOR detects changes in VOUT. Proposed System

27. Survivor – System Proposed System

28. Survivor – Simulation Results Proposed System

29. High PSRR Scheme – A Simple Model for PSRR Proposed System

30. High PSRR Scheme – System Proposed System • Path ‘a’ attenuated by RC filter. • R can be very high without loss of headroom or efficiency (1/RC ≈ BWA). • Path ‘b’ attenuated by cascode.

31. High PSRR Scheme – Simulation Results Proposed System • Simulation at worst case bias: • VDD = 1.6V • Iload = 10mA • PSRR = -40dB

32. Contributions

33. Conference Publications • V. Gupta, G. A. Rincón-Mora, “A low dropout, CMOS regulator with high PSR over wideband frequencies,” IEEE International Symposium on Circuits and Systems, Kobe, Japan, 2005. • V. Gupta, G. A. Rincón-Mora, “Predicting and designing for the impact of process variations and mismatch on the trim range and yield of bandgap references,” IEEE International Symposium on Quality Electronic Design, Santa Clara, CA, 2005. • V. Gupta, G. A. Rincón-Mora, P. Raha, “Analysis and design of monolithic, high PSR linear regulators for SoC applications," IEEE International SOC Conference, Santa Clara, CA, 2004. • V. Gupta, G. A. Rincón-Mora, “Predicting the effects of error sources in bandgap reference circuits and evaluating their design implications,” IEEE International Midwest Symposium on Circuits and Systems, Tulsa, OK, 2002. Contributions

34. Schedule Future Work • Currently in the middle of Design Cycle 1. • Have submitted prototype design of bandgap reference circuit for fabrication. • Have submitted prototype of Survivor for fabrication.

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