General Purpose Charge Readout Chip Nikhef, 4-5 January 2006

1. General Purpose Charge Readout ChipNikhef, 4-5 January 2006 • Outline • Motivations and specifications • Architecture & building blocks • Programmable Charge Amplifier • Time-interleaved Multi-Channel A/D Converter • Digital filtering and Signal Feature Extraction • Project Milestones

2. Requirements of the front-end and readout electronics for High Energy Physics Experiments: low power, high speed, high density, low mass, radiation tolerance These requirements can only be met by highly integrated systems implemented with very deep submicron CMOS technologies. The volumes of ICs required for a typical HEP detector remain low <1Mch Non Recursive Engineering (NRE) costs are more and more dominant for high energy physics. Development of standard chips capable of handling a wide range of high energy physics applications, in order to warrant the NRE expenditure. Likely this polyvalence will be obtained through an increased level of programmability. Motivations & Specifications 1/2

3. A general purpose charge readout chip number of readout channels: 32 or 64 programmable charge amplifier: sensitive to a charge in the range: ~102 - ~107 electrons Input capacitance: 0.1pF to 10pF high-speed high-resolution A/D converter: sampling rate in the range 40MHz - 160MHz; programmable digital filter for noise reduction and signal interpolation; a signal processor for the extraction and compression of the signal information (charge and time of occurrence). Motivations & Specifications 2/2

4. Charge Readout Chip Block Diagram Anti-Aliasing Filter Anti-Aliasing Filter Anti-Aliasing Filter Signal Processor Signal Processor Signal Processor Data Compression Data Compression Data Compression Multi-Acq Memory Multi-Acq Memory Multi-Acq Memory Charge Amplifier Charge Amplifier Charge Amplifier ADC ADC ADC I N T E R F A C E Hit Finder • Maximize S/N • reduce quantization error • reduce signal bandwidth • Correct for crosstalk and common mode noise • Optimum pulse shaping for extraction of pulse features Feature Extaction Histogrammer 32 / 64 Channel

5. Milestone I (Q4 2006) ⇒ Programmable Charge Amplifier (prototype) 16 channel charge amplifier + anti-aliasing filter. Milestone II (Q2 2007) ⇒ 10-bit multi-rate ADC (prototype) 4-channel 10-bit 40-MHz ADC. The circuit can be operated as a 4-channel 40-MHz ADC or single-channel 160-MHz ADC. Milestone III (Q2 2008) ⇒ Charge Readout Chip (prototype) This circuit incorporates 32 (or 64) channels. Milestone IV (Q2 2009) ⇒ Charge Readout Chip (final version) Project Milestones

6. up Phase Detector Charge Pump down Ref. Clock (40 MHz) Vctrl Voltage Controlled Delay Line CLK CLK A A A A fa fa A fb 4-Channel 40-MHZ ADC B fb fc A A B B fc CLK fd 2-Channel 80-MHZ ADC A fd fa C fb C A C C fc A 1-Channel 160-MHZ ADC C fd D C D A D Multi-Channel Time-InterleavedA/D Converter Upgrade of ALTRO ADC A/D A/D A/D A/D A/D

7. Low-noise Amplifier (CMOS 0.13mm) Increased gm • Better ENC (Should ideally improve by ca. 20% per CMOS Generation) • Low Supply Voltage limits SNR • Smaller Dynamic Range • Rail to Rail Design • Invest Power to improve SNR • Big Capacitors • Design Shaping Circuit for Low Noise • Reduced Gate Oxide Thickness • Gate Tunneling Current • Radiation Tolerance • Short Channel Effects • Hot Carrier Stress – Reliability, Noise • Velocity Saturation

8. Low-noise Amplifier (CMOS 0.13mm) Architecture: CSA + Semi Gaussian Shaper Vbias 4th Order Low Pass Filter Rf (MW) Vgs Z(s) Rf/20 Cf Idet -20 • Idet - - Cf *20 The Resistance of the Feedback Element is a function of its Gate to source Voltage • Vgs is the same for both Transistors  corresponding resistances track each other • The CSA’s input dc level is equal to its output dc level • The Current Gain is -20

9. Low-noise Amplifier (CMOS 0.13mm) Specifications of the first prototype • ENC ca. 300 electronsrms (@12pF Cin) • Peaking Time 100ns • 4th Order Semi Gaussian Shaper • 9mW Power Consumption • Charge Range 0-160fC (negative polarity) • Output Stage: 30pF driving capability • Differential Output • Feedback Resistance of CSA ca. 10 MOhm

10. Low-noise Amplifier (CMOS 0.13mm) Circuit Layout Submitted in December ‘05 The area is dominated by the size of the Capacitors • IBM CMOS 8RF, 0.13 um • CSA Area = 50um X 500um = 0.025mm2 • Total Area per Channel = 0.075mm2 • 16-channel chip  3mm2

11. Sampled time functions that exponentially decrease with increasing time Oscillating sampled time functions Z=1, constant or increasing functions depending on the multiplicity of the pole Sampled time functions that exponentially increase with increasing time Mapping the s-Plane into the z-Plane Im Im jw s-plane z-plane s 0 1 0 Re Re

12. Zero-Pole Locations ALTRO Filter New Filter Im Im z-plane z-plane 1 0 Re 1 0 Re • Complex Zeros and Poles • 18-bit coefficient coding • Real Positive Zeros and Poles • 16-bit coefficient coding

13. Recovery of signal parameters 2/2 Extraction of the pulse features (amplitude and time) V. Buzuloiu et al. Find the pulse features, Amp = F(S1,S2,…) and time = T(S1,S2,..),as quasi-invariants in the sample space A = S ai(fj) Si S3(f) The pulse representation in the sample space S2(f) S1(f)