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A first attempt at learning about optimizing the TigerSHARC code

A first attempt at learning about optimizing the TigerSHARC code. TigerSHARC assembly syntax. What we NOW KNOW!. Can we return from an assembly language routine without crashing the processor? Return a parameter from assembly language routine (Is it same for ints and floats?)

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A first attempt at learning about optimizing the TigerSHARC code

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  1. A first attempt at learning about optimizing the TigerSHARC code TigerSHARC assembly syntax

  2. What we NOW KNOW! • Can we return from an assembly language routine without crashing the processor? • Return a parameter from assembly language routine • (Is it same for ints and floats?) • Pass parameters into assembly language • (Is it same for ints and floats?) • Do IF THEN ELSE statements • Read and write values to memory • Read and write values in a loop • Do some mathematics on the values fetched from memory All this stuff is demonstrated by coding HalfWaveRectifyASM( ) TigerSHARC assemble code 3, M. Smith, ECE, University of Calgary, Canada

  3. Not bad for a first effortFaster than compiler in debug mode Need to learn fromthe compiler onhow to speed code TigerSHARC assemble code 3, M. Smith, ECE, University of Calgary, Canada

  4. How does compiler do it? Look at source code and use mixed mode to show • Warning – out of order instructions displayed TigerSHARC assemble code 3, M. Smith, ECE, University of Calgary, Canada

  5. Many new instructions. Many parallel instruction. Ones inside loop are key How important is coding if conditional jump (NP or not) is predicted or not? BIG 25% 523  435 TigerSHARC assemble code 3, M. Smith, ECE, University of Calgary, Canada

  6. Many new instructions. Many parallel instruction. Ones inside loop are key JMP (NP) 523  435 XR1 not J1 435  491 How important is not using J registers when reading from memory XR1 rather than J1 Now need Condition XALT rather than JLT XCOMP rather than COMP TigerSHARC assemble code 3, M. Smith, ECE, University of Calgary, Canada

  7. Many new instructions. Many parallel instruction. Ones inside loop are key JMP (NP) 523  435 XR1 not J1 435  491and ++ operator 491  435 How important is not using J registers as a destination when reading from memory, and using pointers (*pt++) rather than array ( pt[count]) XR1 rather than J1 Now need Condition XALT rather than JLT XCOMP rather than COMP TigerSHARC assemble code 3, M. Smith, ECE, University of Calgary, Canada

  8. Redoing our code to this point.Note new instructions using XR2 and R2 Try a little thing. R2 = 0 is a constant – move outside loopFound we had already set R2 = 0 outside loop Difference, about half the time – expect improve by 12 cycles Got 491  476 = 15 – timing only accurate to around 10 cycles TigerSHARC assemble code 3, M. Smith, ECE, University of Calgary, Canada

  9. The IF THEN JUMPS in the loop are killing us. Rewrite C++ code into optimized form • Reduce loop size from 6 if > 0 and 7 if < 0 to 4 any way. • Loop size 24 – expect improvement of 48 cycles We go from 476 to 250 cycles That’s 225 cycles or roughly9 cycles saved each time around the loop The jumps were causing us 9 cyclesby disrupting the TigerSHARC pipeline Need to get rid of this jumpand counter increment. Blackfin has hardware loopsDoes the TigerSHARC – Duh!! TigerSHARC assemble code 3, M. Smith, ECE, University of Calgary, Canada

  10. Many new instructions. Many parallel instruction. Ones inside loop are key JMP (NP) 523  435 XR1 not J1 491and ++ operator 435 Remove inner jumpsfrom loop 250 Hardware loop instructions LC0 = loop counter 0 – may only be a few hardware loops possibleSHARC ADSP-21061 – allows 6, Blackfin ADSP-BF5XX – allows 2, so need to still understand software loops IF LC0E  If hardware loop expired, IF NLC0E, if not expired – MM!! TigerSHARC assemble code 3, M. Smith, ECE, University of Calgary, Canada

  11. With hardware loops – 166 cycles!Are we cooking or what! Fine tuning – can we saveN cycles (1 each time round loop)by merging instructions TigerSHARC assemble code 3, M. Smith, ECE, University of Calgary, Canada

  12. Merge those two instructions and use our fancy SIGN-BIT trick for float code We are beatingthe optimized compiler on the float code by afactor of 2 We need 1 cycleto beat thecompiler on theoptimized int code Find in for Assignment 1 I did 138 cycles TigerSHARC assemble code 3, M. Smith, ECE, University of Calgary, Canada

  13. My code passes the tests in 138 cyclesExtra 11 cycles from outside the loop (not worth the time and effort if the loop was larger, or there were more points to process) • Does turning off the Cache make any difference to our code • Find out in assignment 1 TigerSHARC assemble code 3, M. Smith, ECE, University of Calgary, Canada

  14. What is the theoretical maximum speed? • This is something I always work out BEFORE optimizing. • I have a target to meet – normally finish all processing before next sample comes in. • If my code (in theory) can’t meet that target, I need to find a different approach, not spend days optimizing useless code. • In theory – if I have written the code with no hidden stalls – 1 cycle per instruction • 6 instructions outside the loop • 4 instruction inside the loop – N * 4 cycles • Very short loop – read that getting out of very short loop stalls the pipeline – lets add 5 cycles for that • 6 + 24 * 4 + 5 = 107 in theory, 138 in practice • Difference 21 – close enough to being 24, or 1 stall per cycle • Can use the pipeline viewer to find out where the problem is occurring. In a long loop, done 4096 times, might be worth it. TigerSHARC assemble code 3, M. Smith, ECE, University of Calgary, Canada

  15. Most TigerSHARC instructions can be made conditional. WHY? Because doing a NOP instruction (if condition not met) is much less disruptive to the instruction pipeline than doing a JUMP (lose of 9 cycles if jump taken – probably more because of code format) Trying to understand what we have done TigerSHARC assemble code 3, M. Smith, ECE, University of Calgary, Canada

  16. Why mostly conditional instructions? • TigerSHARC has a very deep pipeline, so that conditional jumps cause a potential large disruption of the pipeline • Better to use non-jump instructions which don’t disrupt pipeline, even if instruction is not executed (acts as nop) If (N < 1) return_value = NULL; else return_value = NULL; TigerSHARC assemble code 3, M. Smith, ECE, University of Calgary, Canada

  17. If (N < 1) return_value = NULL; else return_value = value; COMP(N, 1);; IF NJLT, JUMP _ELSE;; J5 = NULL;; JUMP _END_IF;; _ELSE: J5 = value;; If (N < 1) return_value = NULL; else return_value = value; COMP(N, 1);; IF NJLT; DO, J5 = NULL;; IF JLT; DO, J5 = value;; Concept is there – we need to check on whether syntax is correct Why mostly conditional instructions? TigerSHARC assemble code 3, M. Smith, ECE, University of Calgary, Canada

  18. Use J registers for address operations, but store values from memory in XR1 and YR1 WHY? Instructions like this [J1] = XR1;; has the potential to be put in parallel with more operations Trying to understand what we have done TigerSHARC assemble code 3, M. Smith, ECE, University of Calgary, Canada

  19. Hardware – zero overhead loop.About 4 * N cycles better (N is times round the loop) LC0 = N;; Load counter 0 with value N Start_of_loop_LABEL: Loop code here ;; IF NLC0E, JUMP Start_of_loop_LABEL;; NLC0E – Not LC0 expired – essentially Compare LC0 with 2 If less than 2, continue (don’t jump) If 2 or more, then decrement LC0 and jump All sorts of stall issues if not properly aligned –TigerSHARC manual 8-23 CAN’T USE WHEN THERE IS A FUNCTION CALL IN THE LOOP?WHY NOT? – WHAT HAPPENS – NEED TO EXPLORE MORE.Using a software loop when there is a function is okay since calling a function is slow anyway – don’t need efficiency TigerSHARC assemble code 3, M. Smith, ECE, University of Calgary, Canada

  20. Hardware – zero overhead loop.BIG WARNING LC0 = N;; Load counter 0 with value N LC0 uses UNSIGNED ARITHMETIC – MAKE SURE N is not negative, as a negative number has the same bit pattern as a VERY large unsigned number, and the processor will go around the loop for a week We did a check for N <= 0 before entering the hardware loop as another part of our code – so we lucked in – otherise could have big problems. This issue is so important (and time wasting in the laboratories) that will be deducting marks in quizzes and exams TigerSHARC assemble code 3, M. Smith, ECE, University of Calgary, Canada

  21. What’s this XR1, YR1 and R1 stuff • TigerSHARC is designed to do many things at once • So you need appropriate syntax to control it TigerSHARC assemble code 3, M. Smith, ECE, University of Calgary, Canada

  22. What’s this XR1, YR1 and R1 stuff XYR1 = R2 + R3;; does 2 adds XR1 = XR2 + XR3 and YR1 = YR2 + YR3; You can add the X values and not the Y values with this syntax XR1 = R2 + R3;; And NOT with XR1 = XR2 + XR3;; Ugly – but they (ADI) will not change the syntax (DAMY) TigerSHARC assemble code 3, M. Smith, ECE, University of Calgary, Canada

  23. What’s this XR1, YR1 and R1 stuff XYR1 = [J0 += 0x1];; Does a 32-bit fetch and puts the same value into XR1 and YR1. Same as doing XR1 = [J0 += 0];; AND YR1 = [J0 += 1];; at the same time XYR1 = L[J0 +0x2];; Does a dual 64 bit fetch and is the same as doing XR1 = [J0 += 1];; AND YR1 = [J0 += 1];; at the same time TigerSHARC assemble code 3, M. Smith, ECE, University of Calgary, Canada

  24. What’s this XR1, YR1 and R1 stuff XYR1 = [J0 += 0x1];; means XR1 = [J0 += 0];; AND YR1 = [J0 += 1];; XYR1 = L[J0 +0x2];; means XR1 = [J0 += 1];; AND YR1 = [J0 += 1];; at the same time XR1:0 = L[J0 +0x2];; means XR0 = [J0 += 1];; AND XR1 = [J0 += 1];; XYR1:0 = L[J0 +0x2];; means XR0 = [J0 += 0];; AND YR0 = [J0 += 1];; AND XR1 = [J0 += 0];; YR1 = [J0 += 1];; TigerSHARC assemble code 3, M. Smith, ECE, University of Calgary, Canada

  25. What’s this XR1, YR1 and R1 stuff XYR1:0 = L[J0 +0x2];; means XR0 = [J0 += 0];; AND YR0 = [J0 += 1];; AND XR1 = [J0 += 0];; YR1 = [J0 += 1];; XR3:0 = Q[J0 +0x4];; means XR0 = [J0 += 1];; AND XR1 = [J0 += 1];; AND XR2 = [J0 += 1];; AND XR3 = [J0 += 1];; XYR3:0 = Q[J0 +0x4];; means XR0 = [J0 += 0];; AND YR0 = [J0 += 1];; AND XR1 = [J0 += 0];; AND YR1 = [J0 += 1];; AND XR2 = [J0 +=0];; AND YR2 = [J0 += 1];; AND XR3 = [J0 += 0];; AND YR3 = [J0 += 1];; TigerSHARC assemble code 3, M. Smith, ECE, University of Calgary, Canada

  26. Float release generated by C++ compiler– identify new instructions • I see 1 new instruction TigerSHARC assemble code 3, M. Smith, ECE, University of Calgary, Canada

  27. Difference between integer and math operations XYR1 = R2 + R3;; does 2 INTEGER adds XR1 = XR2 + XR3 and YR1 = YR2 + YR3; SYNTAX XR1 = R2 + R3;; And NOT with XR1 = XR2 + XR3;; Use F syntax to make it a float operation XYFR1 = R2 + R3;; does 2 FLOATING adds XFR1 = R2 + R3 and YFR1 = R2 + R3; TigerSHARC assemble code 3, M. Smith, ECE, University of Calgary, Canada

  28. Exercise 1 – needed for Lab. 1 • FIR filter operation -- data and filter-coefficients are both integer arrays – Write in C++ • New_value from Audio A/D, output sent to Audio D/A TigerSHARC assemble code 3, M. Smith, ECE, University of Calgary, Canada

  29. Exercise – needed for Lab. 1 • FIR filter operation -- data and filter-coefficients are both integer arrays -- ASM TigerSHARC assemble code 3, M. Smith, ECE, University of Calgary, Canada

  30. Insert C++ code – for Lab. 1 TigerSHARC assemble code 3, M. Smith, ECE, University of Calgary, Canada

  31. Insert assembler code version (Lab. 2) TigerSHARC assemble code 3, M. Smith, ECE, University of Calgary, Canada

  32. What we NOW KNOW EVERYTHING FOR THE FINAL (REALLY -- ALMOST)! • Can we return from an assembly language routine without crashing the processor? • Return a parameter from assembly language routine • (Is it same for ints and floats?) • Pass parameters into assembly language • (Is it same for ints and floats?) • Do IF THEN ELSE statements • Read and write values to memory • Read and write values in a loop • Do some mathematics on the values fetched from memory All this stuff was demonstrated by coding HalfWaveRectifyASM( ) --  TigerSHARC assemble code 3, M. Smith, ECE, University of Calgary, Canada

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