Understanding the TigerSHARC pipeline

1. Understanding the TigerSHARC pipeline First attempt

2. To be tackled today • Viewing the TigerSHARC pipeline • Pipeline stages • Instruction fetch operations • Meaning of pipeline symbols • Stall in the IALU and on the J- data bus • Simple exercise on the COMPUTE block First look at TigerSHARC pipeline

3. Test environment – main.cpp First look at TigerSHARC pipeline

4. Test environmentPipeline.asm First look at TigerSHARC pipeline

5. Using the “Pipeline Viewer” • Available with the TigerSHARC simulator ONLY • VIEW | Debug Windows | Pipeline viewer • F1 to F4 – instruction fetch unit pipeline • PD, D, I -- Integer ALU pipeline • A, EX1, EX2 – Compute Block pipeline First look at TigerSHARC pipeline

6. Fetch (instruction) pipeline F1 – F4 deals with QUAD words Other pipe stages work with “instruction(s)” and are “instruction driven” • This pipe fetched memory quad words and “parses” them into instruction lines • F1 – Fetch address issued to memory AND BTB • BTB predicts whether the next fetch is sequential or a branch with “prediction taken” should take place • By F4 stage, the memory quad word “returns” (sic) to IAB, which parses “individual instruction(s) which program sequencer sends to execution units First look at TigerSHARC pipeline

7. Integer pipeline • PreDecode • Sequencer issues predicted jumps, • or stalls for IALU dependency (if needed). • IALU read from J/K register files • Starts address/instruction calculation First look at TigerSHARC pipeline

8. Integer pipeline • PreDecode • Decode • Recognizes mispredicted condition jumps for IALU condition • Issues stalls for compute block dependency • IALU complete address/instruction calculations • IALU update status (IALU conditions) First look at TigerSHARC pipeline

9. Integer pipeline • PreDecode • Decode • Integer • IALUs (J and K) issue addresses for memory access First look at TigerSHARC pipeline

10. Compute pipeline • PreDecode • Decode • Integer • Access • IALUs receive acknowledgement to begin memory access First look at TigerSHARC pipeline

11. Compute pipeline • Access • Execute 1 • Compute blocks begin calculations • Data is transferred on J/K buses • Execute 1 and 2 (sic) • Mis-predicted conditional jumps based on compute block recognized • Compute blocks complete calculation and update status (based on compute block calculations) • IALUs complete execution of memory access instructions First look at TigerSHARC pipeline

12. Pipeline symbols Control - click First look at TigerSHARC pipeline

13. Pipeline viewer stops “after” executing instruction (one or many cycles) First look at TigerSHARC pipeline

14. Other material comes from the call to “Pipeline( )” from “C++” ABORT Question – aren’t all “jumps” predicted by default? First look at TigerSHARC pipeline

15. Pipeline shows quad fetches from memory 3 instructions = 4 words J2 =left_buff; which is turned into J2 = 0xYYYYYYYY by linker requires 64 bits. First look at TigerSHARC pipeline

16. Fetches occurring “far ahead” of instructions Invalid fetches Means “garbage fetches” occurring?All required instructions have already been fetched? Question – where are instructions being stored?ActivateCache( ) did something? First look at TigerSHARC pipeline

17. Stalls occurring • PreDecode • sequencer issues predicted jumps, • or stalls for IALU dependency (if needed). • Starts address/instruction calculation STALL Stall released First look at TigerSHARC pipeline

18. Stall released Integer – issue addresses for memory access STALL Stall released First look at TigerSHARC pipeline

19. NOTE 32 –bit instruction 0x080288 64-bit instruction 0x080289 / 8A 32 bit instructions 0x08028B 0x08028C etc Manual says “pipeline viewer” shows“bits of instruction” in F1 to F4 And exact instructions in other phases First look at TigerSHARC pipeline

20. Additional stalls for IALU dependency WAIT First look at TigerSHARC pipeline

21. Regular pattern of stalls after this – why? • Perhaps because we are getting “4 values” fetched from data memory each time? First look at TigerSHARC pipeline

22. Exercise – Explain the following – also see next slide Why are NOPSbeing fetched and not XR instructions? What dependency is causing the stall?When is the dependency resolved? Is the stall released before or after the dependency is resolved? What are the bubbles for? Why the wait? First look at TigerSHARC pipeline

23. Example – picture 2 First look at TigerSHARC pipeline

24. Tackled today • Viewing the TigerSHARC pipeline • Pipeline stages • Instruction fetch operations • Meaning of pipeline symbols • Stall in the IALU and on the J- data bus • Simple exercise on the COMPUTE block First look at TigerSHARC pipeline

25. First look at TigerSHARC pipeline

26. First look at TigerSHARC pipeline