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Analog & Mixed-Signal Test Where are we going to?

analogue embedded testing. The question is?. Analog & Mixed-Signal Test Where are we going to?. or The question should be:. Analog & Mixed-Signal Test Where do we have to go?. The answer is:. We are going to where we have to go. That is. On-Chip Test Manager. Stimuli generation

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Analog & Mixed-Signal Test Where are we going to?

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  1. analogue embedded testing The question is? Analog & Mixed-Signal Test Where are we going to?

  2. or The question should be: Analog & Mixed-Signal Test Where do we have to go?

  3. The answer is: We are going to where we have to go ... That is ....

  4. On-ChipTest Manager • Stimuli generation • Result compression • Precision timing • Diagnostic • Power manager • Test Control • Support for board & system level DfT & BISTed ICs Low Bandwidth external interfaces DISTRIBUTED or CONCENTRATED? Memory (BISTed) External ATE Digital Tester Low cost-per-pin Limited speed Limited accuracy Logic (BISTed) Mixed-Signal (BISTed) I/O & Interconnects (BISTed) IC High Bandwidth internal interfaces

  5. Why?

  6. The SUPER-COSTLY-TESTER Era The ATE industry is creating SUPER-COSTLY-TESTERs as a demand of the IC manufacturers. Memory: • Very high amount of data. Represents 40% of improvements in testers Mixed-Signal Instrumentation: • Higher bandwidth, higher sampling rates, higher accuracy, lower noise, etc. • RF and audio circuits a major challenge, more when noisy digital circuitry is also present. DUT to ATE interface: • Higher pin-counts, high frequency & performance probes and sockets. • No degradation of tester accuracy and noise.

  7. Test cost Is in fact a money problem? May be. Perhaps not ! However …

  8. Source: SIA Roadmap uP Memory digital Devices30% per year RF MixedSignal ATE: +12% per year aprox. Tester timing errors Bandwidth Gap between ATE and signals On-Chip!!!!!

  9. Test Complexity More to Test but Less Test Access!!!!! Test Development and Application time may become prohibitive

  10. The KEY AREAS • Standard Test Access Mechanism • 1149.4 well-accepted • P1500 needs MS extension • Structured Test Planning: • Depends on the available resources (DSP, uP, Memory, etc.). • DfT & BIST

  11. DfT & BIST • Can be emulated on-chip a complete external testing? • NO for most of the functional testing cases.SO, • Functional testing must be reduced. • Reduce costly or non-practical on-chip tests • Structural test is a clear powerful complement to functional testing. • Structural test related to the I/O functional behavior and performance are of main interest.

  12. CONCLUSIONS MORE RESEARCH IN THE KEY AREAS IS NEEDED!!!! So, Is in fact a money problem? May be. Perhaps not? YES!!!!! Because Research can not be disaggregated from money.

  13. There is no other way to cope with the cost and complexity of future ICs. • Do not try to emulate a complete external testing: This is not practical in most cases. Functional testing must be reduced. • Reduce costly or non-practical on-chip tests • Structural test is a clear powerful complement to functional testing (OBIST) • Structural test related to the I/O functional behavior • Accessing: Yes, but non-intrusive (sw-opamp)

  14. KEY AREAS • Re-usable and structured DfT & BIST techniques • Reduce I/O data rate requirements, • Enable low pin count testing, and • Reduce the dependence on expensive instruments. • Structured Test planning • Enable hierarchical testing • Enable the re-use of on-chip resources (DSP, uP, etc.) • Facilitate parallel testing • etc. • Standardized Test Access Mechanism

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