EE 5323 Project 16 Bit Sklansky Adder Phase 2 Report

1. EE 5323 Project16 Bit Sklansky AdderPhase 2 Report Yuan Xu 4139225 xuxxx488@umn.edu

2. Contents • Summary • Design Optimization & Changes • Waveforms of test cases • Schematic & Layout • maximum operating frequency VS. VDD • Power consumption at the maximum operating frequency VS. VDD • Netlist • DRC,LVS results

3. Summary • The goal of this project is to realize 16bit Sklansky adder by using static CMOS devices. • Sklansky adder belongs to tree adder family. • The difference between Sklansky adder and other tree adders is prefix network. • Compare to other tree adders, Sklansky adder has minimum logic levels, wiring tracks, but maxinumfanout. Also, it has largest delay at the same condition.

4. Summary Structure of 16 bit Sklansky Adder (Black square is dot operator Grey square is empty dot operator White triangle is buffer)

5. Reference List • D.Harris, “ A Taxonomy of Parallel Prefix Networks, Signals ”, Systems and Computers, 2003. Conference Record of the Thirty-Seventh Asilomar Conference on, 2, 2213-2217 Vol.2,2003 • J. Sklansky, “Conditional-sum addition logic,” IRE Trans. Electronic Computers, vol. EC-9, pp. 226-231, June 1960. • J M. Rabaey, A. Chandrakasan, B. Nikolic, “ Digital Integrated Circuits-A Design Perspective (Second Edition)”, Prentice Hall, 2003 • Wu,S.D.,Chun-Chi Tsai, Yang,M, “A VLSI Layout Legalization Technique Based on a Graph Fixing Algorithm”, VLSI Design, Automation and Test, 2006 International Symposium on, 2006, 1-4 • Mason, J.S.B.; , "Layout tecbmques for mixed-signal VLSI design," Systems on a Chip (Ref. No. 1999/133), IEE Colloquium on , vol., no., pp.8/1-8/11, 1999

6. Design Optimization and changes • Sizing the gate to minimum size (90nm) reduces power • By using bubble shifting, we save totally 28 inverters, and 4 inverters on the critical path • Adding the buffer can effectively reduce delay. Setting stage=1, fanout=4 • Minimizing each block to reduce area • Combining VDDs of different devices to reduce area

7. Design Optimization and changes • Combining Nwell and Pwell of different devices to simplify the layout • Using fewer metal layers (2 layers) to reduce complexity and capacitance • Changes: Fixing some flaws (body not connected to ground) in schematic

8. Waveforms of test cases • Worst case: For Sklansky adder, the worst case happens when inputs are 7FFF+0001. Since G will propagate from A_0 to S_15 which is the critical path.

9. Waveforms of test cases from layout • Worst case 7FFF+0001 • A_0-A_15 B_0-B_15 Cout,S_0-S_15,

10. Waveforms of test cases from layout • Delay from A_0 to S_15 is 8.946E-10S

11. Waveforms of test cases from layout • FFFF+0002 • A_0-A_15 B_0-B_15 Cout,S_0-S_15,

12. Waveforms of test cases from layout • Other cases(1111 0000, 0011 0045, 11FF EDAB, 9782 1234, AABB 5432, 1543 78AB, • FFFF FFEE, 1AB2 F182, 1BCD 2525,2312+4567,1278+AC00,FFFF+FFFF,4444+7777, 1894+2636,CC53+D126 • A_0-A_15 B_0-B_15 Cout,S_0-S_15

13. Final schematic of adder

14. Final LayoutArea: 37.4 μm×11.8μm

15. Maximum operating frequency for different VDD! from layout

16. Power consumption at the maximum operating frequency at different VDD

17. Circuit netlist from layoutandmodified runtestadder16b_xxx.spSee attached filesNetlist name is : new_16_bit_adder • Sizing • NMOS: L=50nm, W=90nm • PMOS: L=50nm, W=135nm • Temperature: 25°C

18. DRC Pass

19. LVS Pass