CMOS ET Workshop, Vancouver, 23-25 September 2009

1. CMOS ET Workshop, Vancouver, 23-25 September 2009

2. CMOS ET Workshop, Vancouver, 23-25 September 2009 Outline Variability: Issue and Main source FDSOI: One technology solution UCO: the Power Switch that reduces the leakage current variability Conclusion

3. CMOS ET Workshop, Vancouver, 23-25 September 2009 Variability-induced issues?

4. CMOS ET Workshop, Vancouver, 23-25 September 2009 Technological variations induce electrical fluctuations. Channel dopant fluctuation: main source of variability in CMOS on Bulk Si.

5. CMOS ET Workshop, Vancouver, 23-25 September 2009 Outline Variability: Issue and Main source FDSOI: One technology solution UCO: the Power Switch that reduces the leakage current variability Conclusion

6. CMOS ET Workshop, Vancouver, 23-25 September 2009 Simulations: towards FDSOI !

7. CMOS ET Workshop, Vancouver, 23-25 September 2009 FDSOI improves variability

8. CMOS ET Workshop, Vancouver, 23-25 September 2009 FDSOI: a lasting solution against variability

9. CMOS ET Workshop, Vancouver, 23-25 September 2009 Inter-die variability : impact of TSi VT variations at the wafer level are governed by SCE and sL: Thinning TSi is effective to limit the impact of sL on sVt.

10. CMOS ET Workshop, Vancouver, 23-25 September 2009 Scaling rules for FDSOI

11. CMOS ET Workshop, Vancouver, 23-25 September 2009 Local, inter-die and total VT variability The total VT variability is significantly improved in our FDSOI devices: Aggressive scaling performed with respect to bulk and FinFET technologies; Similar VT variability between FDSOI 32nm and bulk 65nm.

12. CMOS ET Workshop, Vancouver, 23-25 September 2009 Outline Variability: Issue and Main source FDSOI: One technology solution UCO: the Power Switch that reduces the leakage current variability Principle of operation and Description of the UCO Measurement results of UCO testchip and Monte Carlo simulations Conclusion

13. CMOS ET Workshop, Vancouver, 23-25 September 2009 Ultra Cut-Off (UCO) Power switch transistor The UCO power switch is: a Low-VT transistor; polarized to its point of minimum leakage. Very high ION/IOFF ratio. When reverse-polarizing the gate of the PS: - The subthreshold current ISTH decreases exponentially, - But the �gate-induced drain leakage� IGIDL and the gate leakage IG currents exponentially increase. => There exists a point of minimum leakage.When reverse-polarizing the gate of the PS: - The subthreshold current ISTH decreases exponentially, - But the �gate-induced drain leakage� IGIDL and the gate leakage IG currents exponentially increase. => There exists a point of minimum leakage.

14. CMOS ET Workshop, Vancouver, 23-25 September 2009 UCO salient feature The gate-bias circuit automatically polarizes the gate of the PS to its point of minimum leakage, whatever the: Temperature (figure below), Process variations, Supply voltage. The total leakage current is minimized when: ISTH � IGIDL+IG, ITOT � 2*(IGIDL+IG)

15. CMOS ET Workshop, Vancouver, 23-25 September 2009 Implementation The auto-bias circuit consists of: two reference transistors MA and MB, respectively representing ITOT and 2*(IGIDL+IG), a current sense amplifier to compare those currents, a charge pump to generate the bias voltage VP. The penalty area overhead is equal to 4% for a 5500�m large PS (ION=100mA).

16. CMOS ET Workshop, Vancouver, 23-25 September 2009 Operation When the EN signal goes low, the circuit is activated. Initially, the sense amplifier generates UP impulses to command the charge pump to increase the VP voltage. Then, UP and DN impulses alternate and the VP voltage reaches a mean value.

17. CMOS ET Workshop, Vancouver, 23-25 September 2009 Outline Variability: Issue and Main source FDSOI: One technology solution UCO: the Power Switch that reduces the leakage current variability Principle of operation and Description of the UCO Measurement results of UCO testchip and Monte Carlo simulations Conclusion

18. CMOS ET Workshop, Vancouver, 23-25 September 2009 Measurements in temperature Measurements in temperature have been performed from -40�C to +125�C. The VP value evolution with temperature is in accordance with simulation results. The measured leakage current gain is lower than found in simulation.

19. CMOS ET Workshop, Vancouver, 23-25 September 2009 Room temperature measurement results Measurements have been performed on 46 chips at room temperature: The mean VP value is equal to 1.53V (VPopt=1.57V in simulation); The standard deviation is 30mV (36mV in simulation). Lower figure shows that: the UCO circuit might effectively compensate for parameters variations, but the number of measured values is too small to tell.

20. CMOS ET Workshop, Vancouver, 23-25 September 2009 Monte Carlo simulations (corners + mismatch) The optimal bias voltage VP depends on the initial PS leakage current (sVP = 20mV). The variability of leakage currents is reduced from 21x to 4x: The Relative Standard Deviation is divided by 2.

21. CMOS ET Workshop, Vancouver, 23-25 September 2009 Outline Variability: Issue and Main source FDSOI: One technology solution UCO: the Power Switch that reduces the leakage current variability Conclusion

22. CMOS ET Workshop, Vancouver, 23-25 September 2009 Conclusion Leakage current is the circuit design parameter the most impacted by variability: RDF is the main source of variability. FDSOI is a real technological solution: Suppression of RDF; TSi fluctuation today very well controlled. Solutions do exist at the circuit level: The UCO automatically polarizes the gate of a Power Switch to its point of minimum leakage; Reduces the leakage variability by a factor 5.

23. CMOS ET Workshop, Vancouver, 23-25 September 2009 Acknowledgement To my colleagues: Designers: Edith Beign�, Olivier Thomas, Marc Belleville Technologists: Olivier Weber, Fran�ois Andrieu

24. CMOS ET Workshop, Vancouver, 23-25 September 2009