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On Rewiring and Simplification for Canonicity in Threshold Logic Circuits

Speaker: Ching -Yi Huang 2011/11/08. On Rewiring and Simplification for Canonicity in Threshold Logic Circuits. Pin-Yi Kuo , Chun-Yao Wang, and Ching -Yi Huang Department of Computer Science, National Tsing Hua University, Hsinchu , Taiwan, R.O.C. Outline. Introduction Rewiring

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On Rewiring and Simplification for Canonicity in Threshold Logic Circuits

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  1. Speaker: Ching-Yi Huang 2011/11/08 On Rewiring and Simplification for Canonicity in Threshold Logic Circuits Pin-Yi Kuo, Chun-Yao Wang, and Ching-Yi Huang Department of Computer Science, National TsingHua University, Hsinchu, Taiwan, R.O.C.

  2. Outline • Introduction • Rewiring • Input grouping and gate decomposition • Target wire removal • Rectification network construction • Simplification • Experimental results • Conclusion Department of Computer Science, National TsingHua University, Taiwan, R.O.C.

  3. Outline • Introduction • Rewiring • Input grouping and gate decomposition • Target wire removal • Rectification network construction • Simplification • Experimental results • Conclusion Department of Computer Science, National TsingHua University, Taiwan, R.O.C.

  4. Threshold Logic (1/2) • A linear threshold gate (LTG) is an n binary input and one binary output function: x1 x2 xn w1 w2 wn T f = 1 if 0if f … … n binary inputs x1, x2, … ,xnwith weights w1, w2, … ,wn a single binary output f a threshold value T x1 x2 x3 f 2 1 1 2 x1 x2 f x3 Threshold logic gate Department of Computer Science, National TsingHua University, Taiwan, R.O.C.

  5. Threshold Logic (2/2) • In comparison to Boolean logic, threshold logic representation has a shorter depth and less nodes in a network. • Threshold logic network v.s. Boolean logic network. 5 nodes and 3 levels 6 nodes and 4 levels Department of Computer Science, National TsingHua University, Taiwan, R.O.C.

  6. Assumption • A threshold logic network is generated by an ILP-based approach [1]. • Each LTG can be expressed in a canonical form which has minimal weights and threshold values. • The weights and threshold value of a threshold function are positive integers [2]. x1 x2 x3 x1 x2 x3 f f 1 2 2 1 -1 2 1 1 y3 = x3’ [1] R. O. Winder, “Threshold Logic.” Ph.D. dissertation, Princeton University, Princeton, NJ,1962. [2] S. Muroga, “Threshold Logic and its Applications”. New York, NY: John Wiley, 1971. Department of Computer Science, National TsingHua University, Taiwan, R.O.C.

  7. Problem Formulation • Given: • A threshold network • An irredundant target wire • Objective: • To rectify the changed functionality of the original threshold network due to the target wire removal by adding threshold logic gates at other locations. Department of Computer Science, National Tsing Hua University, Taiwan, R.O.C.

  8. Problem Formulation n6 n9 n1 1 2 2 2 2 n1 n8 n2 4 a b c h c d g h a b c d g 1 1 1 1 3 1 1 1 1 3 1 1 1 1 1 1 1 n2 n6 4 1 1 2 The rectification network for h’s removal Department of Computer Science, National Tsing Hua University, Taiwan, R.O.C.

  9. Features • Rewire any target wire in a threshold network without changing its functionality. • Only depends on the information of the inputs and weights and the threshold value in each LTG. Department of Computer Science, National Tsing Hua University, Taiwan, R.O.C.

  10. Application • Synthesis and optimization • Generate a threshold network with a new fanin number constraint instead of resynthesizing. Department of Computer Science, National TsingHua University, Taiwan, R.O.C.

  11. Outline • Introduction • Rewiring • Input grouping and gate decomposition • Target wire removal • Rectification network construction • Simplification • Experimental results • Conclusion Department of Computer Science, National TsingHua University, Taiwan, R.O.C.

  12. Rewiring Flow START Input: A threshold network and a target wire Grouping and decomposition Target wire removal Rectification Simplification Output: The synthesized threshold network END Department of Computer Science, National TsingHua University, Taiwan, R.O.C.

  13. Input Grouping and Gate Decomposition • Objective: Separate the inputs and the corresponding weights into different groups. • Step 1. Separate an input whose weight which is equal to the threshold value of the objective gate as a single group. • Step 2. Separate the remaining inputs as another group. • Each group can be extracted as a new decomposition gate. • We then group-wise treat the inputs of an LTG after this grouping process. The decomposition gate a b c 3 1 1 1 d a b c d 1 1 1 3 f f 3 3 3 3 Department of Computer Science, National TsingHua University, Taiwan, R.O.C.

  14. Useless Threshold Logic Gate • Definition 1: A single group LTG is useless if and only if it is an empty gate or it outputs zero for all input combinations. • Theorem 1: Given a nonempty LTG, it is useless if and only if it satisfies the following equation, where n is the number of inputs in this gate. The threshold logic gate is useless because it outputs zero for all input combinations. a b c f 4 1 1 1 Department of Computer Science, National TsingHua University, Taiwan, R.O.C.

  15. Critical Input • Definition 2: An input in a single group LTG is critical if and only if this LTG will become useless after removing this input. • Theorem 2: Given a single group LTG, an input xj with its corresponding weight wj is critical if and only if it satisfies the following equation, where n is the number of inputs in this gate. The gate will become useless after removing a => input a is critical. a b c f 3 2 1 1 Department of Computer Science, National TsingHua University, Taiwan, R.O.C.

  16. Useless Input • Definition 3: An input is useless if and only if the output of this LTG is intact when this input toggles under all input combinations. • Theorem 3: Given an input xj with its corresponding weight wj, xj is useless if and only if it satisfies either EQ(A) or EQ(B) for each input combination, where n is the number of inputs in this gate. The output is intact when input c toggles for all input combinations => Input c is useless a b c f 5 3 2 1 (A) and (B) and Department of Computer Science, National TsingHua University, Taiwan, R.O.C.

  17. Target Wire Removal • Remove the target wire and its corresponding weight from the objective gate directly. • Two possible results. • A normal threshold logic gate. • A useless threshold logic gate. • Rectification at transitive fanout • Rectification at transitive fanin Target wire removal The target wire is critical? No Yes Rectify at the transitive fanout cone? no Yes Case 3 Case 1 Case 2 • Rectification • Threshold value change • Rectification network construction • at each input • AND connection • Rectification • The useless input removal • Rectification network construction • OR connection • Rectification • Threshold value change • Rectification network construction • AND connection Simplification Department of Computer Science, National TsingHua University, Taiwan, R.O.C.

  18. Critical-Effect • Definition 4: A single group LTG has a critical-effect if and only if there exists an assignment such that the output changes from 1 to 0 when each one of its inputs in this assignment changes from 1 to 0. • A vector where an LTG has a critical-effect is called a critical-effect vector. • Theorem 4: Given a single group LTG, the LTG has a critical-effect if it satisfies the following equation, where n is the number of inputs in this gate. a b c d 3 2 1 1 f 5 Department of Computer Science, National TsingHua University, Taiwan, R.O.C.

  19. Rectification Network Construction • Case 1: The target wire is not critical : • The remaining objective gate will not become useless. • Keep the threshold value intact. • Analyze the functionality among all inputs of an LTG with critical-effect vectors for the construction of rectification network. Department of Computer Science, National TsingHua University, Taiwan, R.O.C.

  20. Critical-Effect Vector • We use critical-effect vectors to construct the rectification network in our algorithm. • The loss of a subfunction only occurs when removing a target input which is assumed to be 1 in a critical-effect vector. a b c f 3 2 1 1 Department of Computer Science, National TsingHua University, Taiwan, R.O.C.

  21. Search for the Rectification Network The objective gate and the target wire a. The remaining objective gate The critical-effect vectors d e d e a b c d e Inputs a, band e are found in the critical-effect vector 11001. Inputs a, c and e are found in the critical-effect vector 10101. a b c e a b c e n2 3 1 1 4 6 n2 f n1 f 3 1 1 6 3 1 1 6 1 1 4 6 4 6 n1 10 1 10 10 10 10 The rectification network Department of Computer Science, National TsingHua University, Taiwan, R.O.C.

  22. Rectification Network Construction • Case 2: The target wire is critical, and we rectify it at the transitive fanout cone: • It will cause a useless gate after the removal. a b c d e b c d e b c d e n1 6 4 3 1 1 f f The objective gate and the target wire a The remaining objective gate 4 3 1 1 4 3 1 1 1 1 n1 4 2 4 10 a Department of Computer Science, National TsingHua University, Taiwan, R.O.C.

  23. Rectification Network Construction • Case 3: The target wire is critical, and we rectify it at the transitive fanin cone: The objective gate and the target wire a The remaining objective gate a e a d a c a b a b c d e b c d e n1 6 4 3 1 1 f f 4 3 1 1 4 3 1 1 1 1 1 1 1 1 1 1 2 2 2 2 4 10 4 Department of Computer Science, National TsingHua University, Taiwan, R.O.C.

  24. Outline • Introduction • Rewiring • Input grouping and gate decomposition • Target wire removal • Rectification network construction • Simplification • Experimental results • Conclusion • References Department of Computer Science, National TsingHua University, Taiwan, R.O.C.

  25. a b c d a b c d a b c d a b c d a b c d a b c d Simplification 8 3 5 5 7 6 1 1 2 4 1 1 2 2 1 1 3 4 1 1 1 3 1 1 1 1 1 1 2 3 f f f f f f Decrease the weight in input c Decrease the weight in input d Final Decrease the weights in inputs c, d Decrease the weight in input c Decrease the weight in input d Invalid Invalid Department of Computer Science, National TsingHua University, Taiwan, R.O.C.

  26. Outline • Introduction • Rewiring • Input grouping and gate decomposition • Target wire removal • Rectification network construction • Simplification • Experimental results • Conclusion Department of Computer Science, National TsingHua University, Taiwan, R.O.C.

  27. Experimental Results • The experiments show the logic restructuring capability our rewiring algorithm offers. • We reconstruct a threshold network by using our rewiring algorithm. Department of Computer Science, National TsingHua University, Taiwan, R.O.C.

  28. Experimental Results • We demonstrate the efficiency ofour rewiring algorithm for resynthesizing a threshold networkwith different fanin number constraints. (original:6 -> new:5) [3] R. Zhang, P. Gupta, L. Zhong, and N. K. Jha, “Synthesis and Optimization of ThresholdLogic Networks with Application to Nanotechnologies,” in Proc. DesignAutomation Testin Europe Conf., 2004, pp. 904-909. Department of Computer Science, National TsingHua University, Taiwan, R.O.C.

  29. Outline • Introduction • Rewiring • Input grouping and gate decomposition • Target wire removal • Rectification network construction • Simplification • Experimental results • Conclusion Department of Computer Science, National TsingHua University, Taiwan, R.O.C.

  30. Conclusion • This paper proposes a new rewiring technique for threshold networks • We can directly remove the target wire and then correct it by adding the rectification networks. • A simplification procedure for canonicity that is directly applied to a single LTG is also proposed. • When the threshold logic becomes active in the research of VLSI circuits, this rewiring algorithm will facilitate its applications to logic synthesis and various optimization goals. Department of Computer Science, National TsingHua University, Taiwan, R.O.C.

  31. Thanks for your attention. Department of Computer Science, National Tsing Hua University, Taiwan, R.O.C.

  32. Q & A Department of Computer Science, National Tsing Hua University, Taiwan, R.O.C.

  33. Simplification • The simplification procedure transforms a single group LTG to its canonical representation. • Terminologies • A subvectorof a vector is a vector whose input assumed to be 1 is the proper subset of this vector. • A supervector of a vector is a vector whose input assumed to be 1 is the proper superset of this vector. • A brothervector of a vector is a vector which has the same number of inputs assumed to be 1 as this vector. Subvector Supervector Brothervector Department of Computer Science, National TsingHua University, Taiwan, R.O.C.

  34. a b c d a b c d Simplification 9 8 2 2 3 4 1 1 3 4 f f • Given two single group LTGs, they are functionally equivalent if and only if they produce the same outputs under all critical-effect vectors and the brothervectors of all critical-effect vectors. Department of Computer Science, National TsingHua University, Taiwan, R.O.C.

  35. a b c d a b c d Simplification 9 9 2 2 3 4 2 2 3 4 f f • Given a single group LTG: • Step 1: Ensure that the weights for all inputs and threshold value have no common divisor which is larger than 1. • Step 2: Keep the critical-effect vectors and the brothervector of all critical-effect vectors and records the outputs. a b c d 4 4 6 8 f 18 The LTG before the simplification The LTG after divided by a common divisor Department of Computer Science, National TsingHua University, Taiwan, R.O.C.

  36. a b c d a b c d a b c d a b c d Simplification 9 8 8 9 2 2 3 4 2 2 3 4 1 1 3 4 2 2 3 3 f f f f • Given a single group LTG • Step 3: Iteratively decrease each input weight and the threshold value. Get the new representation after the weight-decreasing operation. • If we decrease a unique weight by 1 in an LTG, the threshold value is decreased by 1 as well. • The inputs with the same weight must be decreased at the same time. • The threshold value is decreased by the number of 1 in these same weight inputs of any critical-effect vectors. The LTG before the simplification The LTG after the input weight decreasing The LTG before the simplification The LTG after the same-weight inputs decreasing Department of Computer Science, National Tsing Hua University, Taiwan, R.O.C.

  37. Simplification • Given a single group LTG: • Step 4: Verify if the functionality between the original LTG and the new LTG intact or not after each weight-decreasing operation. • Step 4-a: If an inconsistency occurs, the weight-decreasing operation is invalid. • Step 4-b: If all outputs are the same, this weight-decreasing operation is valid. • Step 5: Terminate the simplification procedure if any weight-decreasing operation is invalid. Or return to step 3. Department of Computer Science, National TsingHua University, Taiwan, R.O.C.

  38. a b c d a b c d a b c d a b c d a b c d a b c d Simplification 8 3 5 5 7 6 1 1 1 1 1 1 2 4 1 1 3 4 1 1 2 3 1 1 1 3 1 1 2 2 f f f f f f Decrease the weight in input c Decrease the weight in input d Decrease the weights in inputs c, d Decrease the weight in input c Decrease the weight in input d Invalid Invalid Department of Computer Science, National TsingHua University, Taiwan, R.O.C.

  39. Simplification Flow START Decrease the input weight and the threshold value sequentially Input A given LTG Check the validity of this decrement No Divide the LTG by a common divisor Yes Get the critical-effect vectors and their brothervectors Update the LTGand divide the LTG by a common divisor There exists an input weight to decrease? Yes No Output The canonical LTG END Department of Computer Science, National TsingHua University, Taiwan, R.O.C.

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