First Silicon Solutions

2. First Silicon Solutions Providing On-Chip Instrumentation (OCITM) for Today’s Highly Integrated SOC Designs Rick Leatherman 5440 SW Westgate Drive, Suite 240 Portland, OR 97221 rickl@fs2.com www.fs2.com +1-503-292-6730

3. Company Background • FS2 founded in November, 1998 • Located in Portland, Oregon • Design team possesses both strong silicon architecture and test & measurement design experience • Recognized a major shortcoming in the ability of traditional tools to support highly integrated SOC designs.

4. The Problem: Traditional Instruments Will Not Work With The Latest Generation of SOC Designs • Much of the interesting debug information no longer appears at the pins • Important clock and/or status information can be completely hidden • Internal buses • Large number of integrated peripherals • Memory management schemes, caches and out of order processing make disassembly difficult if not impossible w/o hardware assist • Multiple cores have significant amounts of on-chip communications not available at the pins

5. FS2’s Solution is On-Chip Instrumentation (OCITM)

12. On-Chip Instrumentation Provides Scalable Application Specific Development Tool Solutions • Tailored to customer’s toolchain(s) of choice with application specific commands and features • Integrate to source level debugger via thin translation layer to FS2 ABI or MDI. • Support interactive debug with integrated peripherals • Source and task level debug features • Scaled solutions to accommodate available resources • Designers make their own gates vs. features choices • Use all available features in FPGA based proto-typing • Partition to a lesser feature set for final silicon

13. FS2 In-Target System Analyzer JTAG controller box with integrated high speed trace

14. Integrated JTAG/TAP Target Connection

15. The FS2 Product Roadmap Will Involve Enhancing or Developing the Following IP • High Speed Data TAPS • Advanced Trace Collection • Address, data and status collected in trace • Fully qualified real-time collection • On-chip or off-chip storage • Real-time Data Exchange • Observe or stream data in real-time • Configurable Logic Analysis • Ideal for FPGA environments • Supports debug on FPGA and embedded core inter-dependencies • Performance Analysis and Code Coverage • AMBA Bus Analysis • Multi-processor support • Synchronous or independent go and halt • Cross triggers • Interleaved time stamped trace

16. Example Of Real-time Trace Collection Correlated With Source Code

17. Configurable Logic Analysis Support SOC Designs Based On Programmable Logic • Select up to 128 signals to monitor at compile time • Display groups of 32 signals at a time • Can group signals as buses, ports, etc. • On-Chip and Off-Chip configurations • Off-chip greatly reduces required gate count and potential trace depth • Two 32-bit trigger words on-chip/ 4 off-chip • Trigger conditions include high, low, don’t care, rising, falling, either edge • Voltage support: 1.5 to 5.5, auto-configuring • Supports up to 100MHz source-synchronous clock • Trace depth up to 128K (off-chip, 32 channels per frame)

18. Example Of Configurable Logic Analysis Module Display

19. Advanced Functionality: OCI Performance Measurement Plans • Measure activity on buses, caches, execution cores, co processors, interrupts, peripheral device events • Measure absolute event rates like instructions, interrupts, cache hits per unit time, or tracepoints • Measure durations like time from one tracepoint to another, interrupt latencies, bus access latencies, DMA transfer times, loop times of network packet processing, block processing of DSP input data, etc. • Measure device utilization like percentage of total bus bandwidth utilized, hit/miss ratios on I and D caches, DRAM pages, branch target caches, plus percentage time the processors is stalled waiting for a resource such as a cache or bus or execution unit. • Measure the stall of each processor caused by a lockout of a shared resource.

20. Advanced Functionality: Function Level Performance Analysis Display

21. Advanced Functionality: OCI AMBA Bus Analyzer Plans • Capture AMBA bus activity in real-time • OCI multiplexes and transmits 80 bits of AHB bus cycle information to probe • Up to 8 additional inputs may be attached to any node in the SoC • Probe recovers original clock-by-clock bus state • Probe aligns bus cycle phases to allow triggering using combinations of address and data • Trace buffer stores either clock cycles or valid bus transfer cycles • Trace buffer stores up to 128K clock or bus cycles • Four triggers recognize 1, 0, X, rising edge, falling edge, either edge, double high, double low, or no-change (same state for two successive samples)

22. Advanced Functionality: OCI AMBA Bus Analyzer Plans • Four trigger states, one 32-bit event counter/timer • Trigger conditions include 88-bit bus events, Event counter/timer value and Trigger state • Actions include Trigger CLAM, Trace control (start, stop, single), Trig Out control (pulse, assert, negate), Counter control (increment, start, stop, clear), and Goto state • Automatic trace clock frequency measurement allows displaying time in either seconds or clocks • Variable logic threshold configured automatically using VIO signal or manually • Trigger position variable from 1/512 to 511/512 of the trace buffer depth

23. FS2 Is Moving Aggressively To Provide Multiprocessor OCI Support Merging OCI blocks to be controlled by a single JTAG TAP Control signals for multi-core cross triggering and synchronous go, halt and breaks Multi-core trace alignment with timestamp On-chip filtering to prevent processor stalls Ultra high speed data TAP technology Controller box API’s to support multi-core trace The FS2 controller box can handle multiple instantiations of a source level debugger

24. Reducing Time-to-Market For Silicon and Software Integrates with hardware emulation environment Supports FPGA based prototypes Primary tool for first silicon debug Stimulus for passive test equipment Access to BIST Tcl/tk scripts for fast go/no-go testing Strengthens tool message Demonstrated time to market benefits Bundled into evaluations platforms Application code development H/W and S/W integration Performance tuning

25. FS2 Business Model

26. Questions Rick Leatherman First Silicon Solutions, Inc. Portland Oregon, USA Rickl@fs2.com 503.292.6730 x102