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Verilog Overview

Verilog Overview. Prof. MacDonald. Verilog Overview. C-Like Language used to describe hardware VHDL is main competitor VHDL is more rigorous and typed VHDL takes longer to write VHDL is used by 50% of USA Verilog was originally owned by Cadence Now an open language with standards

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Verilog Overview

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  1. Verilog Overview Prof. MacDonald

  2. Verilog Overview • C-Like Language used to describe hardware • VHDL is main competitor • VHDL is more rigorous and typed • VHDL takes longer to write • VHDL is used by 50% of USA • Verilog was originally owned by Cadence • Now an open language with standards • Used for ASIC design and FPGA programming • Verilog HDL : A Guide to Digital Design and Synthesis by Samir Palnitkar

  3. Simple Example module counter (reset, clk, count, top); input reset, clk; output [3:0] count; output top; reg [3:0] count; wire top = count == 4’b1111; always @(posedge clk) if (reset) count <= 4’b0; else count <= count + 1; endmodule

  4. Simple Example module counter (reset, clk, count, top); input reset, clk; output [3:0] count; output top; reg [3:0] count; wire top = count == 4’b1111; always @(posedge clk) if (reset) count <= 4’b0; else count <= count + 1; endmodule

  5. Simple Example module counter (reset, clk, count, top); input reset, clk; output [3:0] count; output top; reg [3:0] count; wire top = count == 4’b1111; always @(posedge clk) if (reset) count <= 4’b0; else count <= count + 1; endmodule

  6. Simple Example module counter (reset, clk, count, top); input reset, clk; output [3:0] count; output top; reg [3:0] count; wire top = count == 4’b1111; always @(posedge clk) if (reset) count <= 4’b0; else count <= count + 1; endmodule

  7. Simple Example module counter (reset, clk, count, top); input reset, clk; output [3:0] count; output top; reg [3:0] count; wire top = count == 4’b1111; always @(posedge clk) if (reset) count <= 4’b0; else count <= count + 1; endmodule

  8. Simple Example module counter (reset, clk, count, top); input reset, clk; output [3:0] count; output top; reg [3:0] count; wire top = count == 4’b1111; always @(posedge clk) if (reset) count <= 4’b0; else count <= count + 1; endmodule

  9. Simple Example module counter (reset, clk, count, top); input reset, clk; output [3:0] count; output top; reg [3:0] count; wire top = (count == 4’b1111); always @(posedge clk) if (reset) count <= 4’b0; else count <= count + 1; endmodule

  10. Simple Example module counter (reset, clk, count, top); input reset, clk; output [3:0] count; output top; reg [3:0] count; wire top = count == 4’b1111; always @(posedge clk) if (reset) count <= 4’b0; else count <= count + 1; endmodule

  11. Testbench circuit under test (CUT) counter.v any other inputs monitors reset gen clock gen synthesizable code unsynthesizable code – artificial and for verification only waveform gen tb.v testbench

  12. Testbench `timescale 1ns/1ps module tb (); reg clk, reset; wire [3:0] count; counter counter1 (.clk(clk), .reset(reset), .count(count), .top( )); initial clk = 0; //clock generator initial forever #10 clk = ~clk; //clock generator initial //main stimulus block begin reset <= 1’b1; #500 reset <= 1’b0; #1000$finish; end always @(count) $display("counter value is now %x at time %t",count, $time); initial begin $dumpfile("verilog.dmp"); $dumpvars; end endmodule

  13. Output log (verilog.log) Compiling source file "tb.v" Compiling source file "counter.v" Highest level modules: tb counter value is now 0 at time 5 counter value is now 1 at time 1005 counter value is now 2 at time 1015 counter value is now 3 at time 1025 counter value is now 4 at time 1035 counter value is now 5 at time 356085 counter value is now 6 at time 356095 counter value is now 7 at time 356105 counter value is now 8 at time 356115 counter value is now 9 at time 356125 counter value is now a at time 356135 counter value is now b at time 356145 counter value is now c at time 356155 counter value is now d at time 356165 counter value is now e at time 356175 counter value is now f at time 356185 counter value is now 0 at time 356195 counter value is now 1 at time 356205 VERILOG interrupt at time 356210 C1 > 0 simulation events (use +profile or +listcounts option to count) CPU time: 0.2 secs to compile + 0.1 secs to link + 6.1 secs in simulation End of VERILOG-XL 3.40.p001 Nov 16, 2004 09:58:09

  14. Output Waves

  15. Design Abstraction • High Level Behavioral • C or Matlab • Register Transfer Level (RTL) • describes logic design with C like constructs • modern definition is that RTL is synthesizable • Gate level (netlist) • describes design as a collection of logic gates connected together – product of synthesizing RTL code • Transistor level (circuit design) • gates (primitives) used in synthesis • details are hidden “under the hood” from logic designers

  16. Simple Design Flow (ASIC/FPGA) Specification Architecture RTL Coding Simulation standard cell library Synthesis Place, Route, and Timing

  17. Verilog Data Types • Combinatorial logic is represented by wire data type • must be driven by an output or continuous assignment • can be connected to any number of inputs • reg can represent either combinatorial or sequential • regs in verilog are not necessarily flip-flops • are defined by procedural blocks (initial or always) • always blocks with “posedge” are sequential • always blocks without “posedge” are combinatorial • Initial blocks are for verification only (testbenches) • Other less common data types include time, real, integer

  18. Verilog Data Types - busses Wires and Regs can be defined as vectors reg [7:0] counter; // 8 bit register of flip-flops wire [10:2] data_bus; // 9 bit bus Can be individually addressed assign output = data_bus[9]; or as a group assign data_bus_out = data_bus;

  19. Verilog Data Types - Numbers Specification by <size>’<base><number> Examples: wire [7:0] data_bus = 8’hFF; // 8 bit hex number wire [7:0] data_bus = -1; // unsized – eight ones wire [7:0] data_bus = 0; // unsized – eight zeros wire [7:0] data_bus = 8’d10; // 8-bit decimal number wire [7:0] data_bus = 8’b1010_1010; // 8-bit binary Underscore can be used for clarity

  20. Arithmetic Operators - +, -, /, *, % • Arithmetic operators imply ALU in synthesis • Plus operator for addition + • Minus operator for subtraction – • Multiply operator for multiplication * • Division operator / (rarely used except in TBs) • Modulus operator % • Ensure input and output precision is appropriate

  21. Logical Operators • Logical operators take two or more boolean vars and provide a single boolean answer. • If input is a vector, then false if all zeros, otherwise true • AND is && • OR is || wire [3:0] inputA = 4’d3; wire inputB = 1’b0; wire C = inputA && inputB; // C = false or zero

  22. Bitwise Operators • Bitwise operators work on each bit of vector • AND & • OR | • NOT ~ • Exclusive OR ^ • Exclusive NOR ~^ (compare) wire [3:0] busA; // 0101 wire [3:0] busB; // 0011 wire [3:0] busAandB = busA & busB; // 0001

  23. Relational Operators • In synthesis, relational operators imply comparison logic • Compare two values and provide a boolean answer • Equality == • Greater than or Equal >= • Greater than > • Not equal != • Less than < • Less than or equal to <= wire [7:0] E = 8’d1111_0111; wire [7:0] F = 8’h0001_0011; assign A = (E == F); // A = 0 assign B = (E != F); // B = 1

  24. Unary Operators • Unary operators act on one input variable • Not – inverts boolean • AND – provides the logical AND of entire bus • OR – provides the logical OR of entire bus • XOR – provides the exclusive OR of entire bus wire A; wire B; wire C; wire [7:0] D = 8’b0000_0001; wire [7:0] E = 8’d1111_0111; wire [7:0] F = 8’h0001_0011; assign A = |D; // A checks for 1s in D assign B = &E; // B checks for 0s in E assign C = ^F; // C is the parity of F

  25. Shift Operators • Shift <<, >> shifts the index of a bus • <vector> >> <number of bits> • Alternative approach is using concatenation wire [3:0] bus = 4’hA; wire [3:0] shifted_bus = bus >> 1; // result is 4’b0101 or 4’h5 wire [3:0] bus = 4’hA; wire [3:0] shifted_bus = {1’b0, bus[3:1]}; // result is 4’b0101

  26. Concatenation Operator • Concatenation Operator {} • Used to splice busses together wire [3:0] A = 4’hA; wire [3:0] B = 4’h5; wire [7:0] C; assign C = {A, B}; // 8’hA5 OR assign C = {1’b0, A, B[3:1]} // for shift with zero insert

  27. Codition Operator (Mux) • Condition operator used to imply muxes assign <variable>= <select> ? <option1> : <option0>; A = B ? C : D; // A = C if B=1 else A = D This construct is dense and can be confusing if over-used.

  28. Continuous Assignment Statements Assignment statements assign values to wires and can be used to describe combinatorial circuits only. Any change on the right side, effects left side immediately if no delay is specified. Delay if specified is un-synthesizable and is for tb only. Ex. wire C; assign #2 C = (A & !B) | (!A & B);

  29. Procedural Blocks Procedural blocks are used to define reg data types and can be used to describe combinatorial or sequential circuits. Procedural blocks can use C-like constructs and begin with always or initial key words. Each procedural block is an like an independent thread – all running in parallel. reg Q; always @(posedge CLK) if (reset) Q <= 0; else Q <= D; CLK D Q

  30. Blocking vs. Non-blocking assignment Regs is procedural blocks can be defined with blocking or non-blocking assignment. Use non-blocking for flops and blocking for combinatorial. always @(posedge CLK) begin if (reset) Q <= 0; else Q <= D; end always @(A or B or Sel) begin if (Sel) Z = A; else Z = B; end Very common interview question

  31. Blocking vs. Non-blocking assignment Problem is that a race condition can exist when defining more than one flip-flop with one always block using blocking assignments. always @(posedge CLK) begin B = A; C = B; end Other solution is to only define one reg in one always procedural block. Less confusing also. 0->0 1->0 0 0->1 1->0 0 C B A D Q D Q clk1

  32. Verilog Procedural Constructs • If-then-else statement • case statement • for loop (not used often in synthesizable code) • while loop (not used often in synthesizable code) • System Calls • $display – dumps variable or string to standard output • $time – tells current simulation time • $stop – finishes the simulation • $dumpvar – creates a waveform file for subsequent viewing

  33. 0 0 1 0 x z 0 0 1 0 1 1 0 0 s0 s1 s2 State Machine Design Example X = 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 0 Z = 0 0 0 0 0 1 0 0 0 0 0 1 0 1 0 0

  34. Alternative Style (moore) Module detector (clk, reset, in, detect) input clk, reset, in; output detect; reg [1:0] state; wire detect = (state == 3); always @(posedge clk) if (reset) state <=0; else case(state) 2’b00 : if (in) state <= 1; else state <= 0; 2’b01 : if (in) state <= 1; else state <= 2; 2’b10 : if (in) state <= 3; else state <= 0; 2’b11 : if (in) state <= 1; else state <= 2; endcase endmodule //

  35. Alternative Style (mealy) Module detector (clk, reset, in, detect) input clk, reset, in; output detect; reg [1:0] state; wire detect = (state == 2) & in; always @(posedge clk) if (reset) state <=0; else case(state) 2’b00 : if (in) state <= 1; else state <= 0; 2’b01 : if (in) state <= 1; else state <= 2; 2’b10 : if (in) state <= 1; else state <= 0; endcase endmodule //

  36. Alternative Style (mealy - 2) Module detector (clk, reset, in, detect) input clk, reset, in; output detect; reg [1:0] state; wire detect = (state == 2) & in; always @(posedge clk) if (reset) state <=0; else case({state,in}) 3’b000 : state <= 0; 3’b001 : state <= 1; 3’b010 : state <= 2; 3’b011 : state <= 1; 3’b100 : state <= 0; 3’b101 : state <= 1; default : state <= 0; // safer // default : state <= 2’bxx; // smaller endcase endmodule //

  37. Test bench test_bench sequence generator state_machine x checker optional stimulus clk z clock generator reset generator circuit under test Only state_machine is synthesizable. All else is for verification purposes only.

  38. Testbench example - psuedocode module test_bench ( ); reg x, clk, reset; // reg declarations initial clk = 0; always forever #100 clk = ~clk; // clk generation initial begin // sequence generation reset = 1; x = 0; #(800) reset = 0; @(negedge clk) x = 0; @(negedge clk) x = 1; @(negedge clk) x = 0; end state_machine U0 (.in(x), .clk(clk), .detect( ), .reset(reset)); endmodule

  39. Testbench Tasks Task adc_transaction ( ); input [7:0] sample; begin @(posedge convert) serial_data <= 0; @(negedge sclk) serial_data <= sample[7]; @(negedge sclk) serial_data <= sample[6]; @(negedge sclk) serial_data <= sample[5]; @(negedge sclk) serial_data <= sample[4]; @(negedge sclk) serial_data <= sample[3]; @(negedge sclk) serial_data <= sample[2]; @(negedge sclk) serial_data <= sample[1]; @(negedge sclk) serial_data <= sample[0]; $display(“just transferred %x from ADC”,input); end endtask

  40. Testbench monitors for the log file always @(posedge tb.dut.data_signal) $display(“%d, %x, %x, %t”, tb.dut.count, tb.dut.var1, tb.dut.var2, tb.dut.var3, $time); These statements provide crucial information about the sim without having to check the waveforms.

  41. Hierarchy Example (contrived) module top (clk, reset, in1, out1, out2) // should be name of file - top.v input clk, reset, in1; // all ports as inputs defined output out1, out2; // all ports as outputs defined reg out1; // outputs can redefine as reg reg [1:0] count; // this is an internal reg wire out2; // outputs can redefined as wire wire [1:0] new_count; // this in an internal wire always @(posedge clk) if(reset) out1 <= 0; else if (new_count == 2’b10) out1 <= in1 && out2; else out1 <= out1; always @(posedge clk) count <= count + 1; assign out2 = in1 && out1; bottom bottom1 (.inA(count), .outB(new_count)); //instantiation endmodule

  42. Hierarchy Example (contrived – page 2) module bottom (inA, outB) // should be name of file bottom.v input [1:0] inA; // all ports as inputs defined output [1:0] outB; // all ports as outputs defined wire [1:0] outB; // outputs can be defined as wire assign outB = inA + 2’b10; // could be combined with wire above endmodule

  43. Synthesis effects Continuous statements always result in combinatorial logic - no flops or latches. wire start; assign start = ready && request;

  44. Synthesis effects Continuous statements always result in combinatorial logic. Here is a 32 bit comparator. Note that the size of the netlist doesn’t necessarily correspond to the number of lines of RTL Wire [31:0] a ; Wire [31:0] b ; Wire the_same ; Assign the_same = (a == b);

  45. Synthesis effects Always block without posedge statement is combinatorial. Always @(D or S or E) begin if (S) A = D; else A = E; end Always @(*) // verilog 2000 begin if (S) A = D; else A = E; end

  46. Synthesis effects Always block without posedge statement is combinatorial. This example will result in an ALU function (potentially very large). Wire [31:0] ina; Wire [31:0] inb; Reg [31:0] out; always @(ina or inb or subract) begin if (subtract) out = ina + (~inb + 32’h1); else out = ina + inb; end

  47. Synthesis effects Always block without posedge statement is combinatorial. This example will result in decoder (8 3-input AND gates). always @(index) case (index) 0: decoder_out = 8’h01; 1: decoder_out = 8’h02; 2: decoder_out = 8’h04; 3: decoder_out = 8’h08; 4: decoder_out = 8’h10; 5: decoder_out = 8’h20; 6: decoder_out = 8’h40; 7: decoder_out = 8’h80; endcase

  48. Synthesis effects Always block without posedge statement is combinatorial. This example will has a problem. All cases must be specified. Here if enable is high, Q=D. What happens if enable is low? Synthesis will add a latch to remember the old value of Q when it is undefined by the if statement. Latches are rarely meant to be used in logic and are a good sign of a problem. Very common interview question always @(*) if (enable) Q = D;

  49. Synthesis effects Always block with posedge clk statement is sequential. This example will result in a simple non-resetable flip-flop. Flip flops that define state or control must be reset, however flip flops in the datapath may be left un-reset if data naturally flows through to initialize. always @(posedge clk) A <= E;

  50. Synthesis effects Always block with posedge clk statement is sequential. This example will result in a synchronous resetable flip-flop. The reset requires the clock edge to take effect. always @(posedge clk) if (!resetN) A <= 0; else A <= E; resetN D Q A clk

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