Reliability of Antifuse-Based Field Programmable Gate Arrays for Military and Aerospace Applications

1. Reliability of Antifuse-Based Field Programmable Gate Arrays for Military and Aerospace Applications John McCollum, Roy Lambertson, Jeewika Ranaweera, Jennifer Moriarta, Jih-Jong Wang, Frank Hawley, and Arun Kundu Actel Corporation 1

2. FPGA Reliability Includes the User • The Design Engineer (user) and his CAE tools are partially responsible for the content of an FPGA • Reliability of an FPGA design is therefore a combination of the manufacturer and the user 2

3. Manufacturer Responsibility • Antifuses are an addition to the base CMOS process • Reliability of the ONO antifuse • There are two states that must be reliable • Open • Short 3

4. N+ Polysilicon Oxide Nitride Oxide N+ Diffusion ONO Antifuse 4

5. ONO Antifuse Photomicrograph 5

6. 6

7. Programmed State of ONO 7

8. Note: No Switch off Heating of Filament Programmed at 5mA 8

9. ONO Antifuse Switch off Test 9

10. Photomicrograph showing failure of Poly Contact, not the Antifuse 10

11. SEDR Curve 90A Thickness Typical is 96A 11

12. Amorphous Silicon Antifuses • Amorphous-Silicon Antifuses allow higher density(Sea of Modules) • Higher performance - Lower Capacitance • Reliability analysis for opens and shorts 12

13. Unprogrammed Antifuse Via to Metal 4 Antifuse Metal 3 13

14. Life of the Universe Data indicates that this line actually turns up 14

15. Programmed Antifuse 15

16. Data showing that switch off of the metal Antifuse is over designed by at least a factor of 2 16

17. SEDR of the Metal to Metal Antifuse No failure SXS shows one failure at 2.85V max spec is 2.75V 17

18. ESD > 2000 Volts • Since BVG (Break Down Voltage) of ONO was lower than gate oxide, no antifuses are connected to pins • ESD thus achieved Class 2 >2000 Volts • Actel however discovered PID (Process Induced Damage) in Fabs • Implanters and Plasma Etchers could produce 20 volts on the wafer and destroy the ONO • Actel worked with the Fabs and solved this problem • Additionally Actel voltage stresses each part at Wafer Sort and Final Test to eliminate all antifuse defects 18

19. Actel Gate Oxide Failures are Rare • Most MOS reliability defects are traditionally Gate oxide Failures • By virtue of the high voltage stresses applied to Actel circuits for programming (even low voltage transistors) there have been very few oxide failures 19

20. Apparent turn up is due to less time to collect long term data 20

21. With ten years of production of Multi-Layer Aluminum the process is very mature even though it has been scaled Early defects related to via failures 21

22. Due to the high level of integration modern ICs have progressed dramatically Note: no failures 22

23. 1000000 100000 10000 1000 100 10 1 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 YIELD Testing ASICs with test vectors of less than 100% can lead to unacceptable failure rates PPM Faults vs Yield 0.7 PPM 0.999 Fault Coverage 0.70 0.80 0.90 0.95 0.96 0.97 0.98 0.99 0.995 0.999 23

24. All tracks All modules All clocks All programming circuits All I/Os All isolation transistors The charge pump All antifuses in the open state All antifuses are stressed A column of circuits is programmed (binning circuit) to verify programming FPGAs are However 100% tested 24

25. During programming a small fraction of antifuses will fail to program • Once the programmer passes a part it is guaranteed to be 100% functional • Tests are performed to verify that the correct antifuse is programmed and is the correct impedance • Additional tests are done to verify that no other antifuse was erroneously programmed or any circuit damage was done 25

26. User Responsibility • CAE tools are reliable in translating RTL code to a logic design, but many pitfalls await the designer • Behavior level code would be less prone to bugs, but it will not be very efficient in silicon use or very fast - hence not much demand • Remember with FPGAs YOU are an IC designer • Following are few examples of pitfalls 26

27. Without “Preserve” VHDL will delete this buffer Q D Q D >CLK >CLK High Skew Clock A lot of emphasis needs to be placed on timing analysis!! 27

28. Register Duplication • In space based applications Register Duplication is to be avoided as SEU can easily create illegal states • VHDL requires you to instantiate the special CLKINT or CLKBUF • Synplify has an option to turn register duplication off 28

29. SEU Prevention • If SEU is a concern, the use of CC Module or TMR techniques are required. Actel tools fully support these techniques in synthesis • The RTSXS family has self refreshing TMR built into every register. It has proven nearly ion proof, such that SEU upsets do not have to be considered in design 29

30. RTSXS is Power-up Friendly • RTSXS have new features to make it power-up friendly while the charge pump is turning on • Outputs are tristated • Logic Modules are in standby • Outputs can be programmed to source or sink 50 A • Once Charge pump has reached operating voltage the modules are activated and the outputs become valid with no glitches 30

31. Synchronous Design • Every FPGA manufacturer will tell their customers “use fully synchronous design” • Yet many designers don’t or manage to avoid fully synchronous design points at critical interfaces • The successful designer will learn his CAE tools and the target FPGA and follow good design practice 31

32. User Testing • FLIP FLOPs can remember their last state up to 24 hours in any MOS Circuit • Set flip flops to the opposite state of the desired power-up state for one hour before power-down followed by the power-up sequence • Power-on reset signals should not be applied until the power supplies have reached spec. 32

33. Summary • Devices and CAE tools have improved tremendously in 30 years. • Very high levels of integration have made systems more reliable • ICs and CAE tools benefit from multiple users to scrub defects from the circuits • FPGAs have made the system designer an IC designer - ultimately the system reliability rests with him 33