CMOS Monolithic Active Pixel Sensors (MAPS) for the ILC

1. CMOS Monolithic Active Pixel Sensors(MAPS) for the ILC

2. Outline Introduction on MAPS MAPS for Particle Physics Parametric test sensors RAL_HEPAPS Source results Irradiation results Flexible APS (FAPS) for ILC. Concept and source results MAPS for ILC

3. Readout control Column-parallel ADCs I2C control Data processing / Output stage CMOS (Monolithic) Active Pixel Sensor (MAPS) (Re)-invented at the beginning of ’90s: JPL, IMEC, … • Standard CMOS technology • all-in-one detector-connection-readout = Monolithic • small size / greater integration • low power consumption • radiation resistance • system-level cost • Increased functionality • increased speed (column- or pixel- parallel processing) • random access (Region-of-Interest ROI readout)

4. CMOS sensors: camera architecture Rolling shutter Snapshot Integration (exposure) and readout are interleaved Integration time given by time between two readouts Simultaneous integration for all pixels, followed by the readout Column-parallel ADCs Column-parallel ADCs Camera control Camera control Data processing / Output stage Data processing / Output stage

5. Potential barriers - + - + - + - + - + - + - + - + - + - + CMOS for 100% efficient detection of charged particles Radiation Metal layers Dielectric for insulation and passivation Polysilicon N+ N+ P+ N+ P-Well N-Well P-Well Concept first proposed in 1999, and published in NIM in 2001 (R. Turchetta et al.) P-epitaxial layer P-substrate

6. MAPS for Particle Physics and Space Science • 2-year PPARC (PPRP) funded programme to develop the underpinning technology. Started June 2003. Total funding of £300k over 2 years. • 5 institutes: • University of Liverpool  HEP • University of Glasgow  HEP • University of Leicester  SS • University of Birmingham  SS • CCLRC-RAL with 3 departments: Instrumentation, Space Science and Particle Physics • 4 axes. • Pixel architecture: noise, analogue memory, data sparsification • Radiation resistance • Backthinning: for EUV detection and minimise material for HEP • Large area sensor

7. Basic Technology MI-3 consortium • Consortium of 11 institutes http://mi3.shef.ac.uk. • Goal: underpinning technology. • University of Sheffield (Department of Electrical and Electronic Engineering) • University of Liverpool (Semiconductor Detector Center) • University of Liverpool (Lab. For Environmental Gene Regulation) • University of Glasgow (Particle Physics Experimental Group) • University of Brunel (Imaging for Space and Applications) • University College, London (Radiation Physics) • Institute for Cancer Research (Royal Marsden Hospital) • University of Surrey (Centre for Vision, Speech and Signal Processing) • University of York (Applied Electromagnetical and Electron Optics Research Group) • MRC Laboratoy of Molecular Biology • CCLRC-RAL (EID, PPD, SSTD) • Started 7/04  end 7/08

8. RAL_HEPAPS family.Sensors for Particle Physics

9. Row decoder/control 3MOS des. A 4MOS des. A CPA des. A FAPS des. A 3MOS des. B 4MOS des. B FAPS des. B 3MOS des. C 4MOS des. C CPA des. B FAPS des. C 3MOS des. D 4MOS des. D CPA des. C Columnamplifiers FAPS des. D Column decoder/control 3MOS des. E 4MOS des. E FAPS des. E 3MOS des. F 4MOS des. F CPA des. D RAL_HEPAPS 2 Parametric test sensor • 4 pixel types • 3MOS • 4MOS • CPA (charge amp) • FAPS (10 deep pipeline) • 3MOS & 4MOS: six different design each of 64x64 pixels at 64x64, 15m pitch, 8m epi-layer  MIP signal ~600 e-

10. Measured noise distributions for a 64x64 pixel test structure. Not corrected for system noise Soft reset RESET ~ Vreset. A factor of ~2 reduction  noise < 20 e- rms Hard reset RESET – Vreset > Vth for reset transistor Noise (ENC in e- rms) Noise (ENC in e- rms) Soft and hard reset Vreset Reset (or kTC) noise is generally the dominant noise source RESET ROW_SELECT Diode Output

11. Number of pixels in a “3x3” cluster HEPAPS2: Some Clusters Source (Ru106) test results. Test made in Liverpool. Cluster in S/N

12. HEPAPS2: Landau distributions

13. RAL_HEPAPS2 3&4 MOS summary • All 12 substructures are working. • 2 had initial problems in fabrication, and no time yet to test them with MIPs. • The 3 structures with 4MOS-GAA have S/N too low for efficient use for MIP detection. • All the 7 others display good S/N for MIP detection. • Test beam just finished (results now to be analysed): • Seed cut determines S/N result • Efficiency, global and as a function of impact point 8 mm epi layer

14. Radiation test. Source results • Noise seems to increase slightly with dose. • Signal decreases with dose. J. Velthuis (Liv)

15. No rad 1014 4-diode15 mm pixel No rad 1015 S/N dependence on impact point. G. Villani (RAL-PPD)

16. ! - + + Radiation test. Summary • Sensors yield reasonable S/N up to 1014 p/cm2 (device simulation confirms) • No efficiency measurement; need testbeam data • 0.35 mm technology in the pixel transistors. Enclosed layout in 3MOS_C • Especially 3MOS_E (4 diodes) looks interesting • Larger capacitance yields larger noise • Four diodes: less dependence of S/N on impact point • After irradiation remains a larger “sensitive area” J. Velthuis (Liv)

17. Amplitude Light pulse Time Flexible Active Pixel Sensor Pulses LED test 10 memory cell per pixel 28 transistors per pixel 20 mm pitch 40x40 arrays Design for the Vertex detector at the International Linear Collider

18. Guidelines Minimize budget material in the central area Keep power dissipation evenly spread and low Keep sensor architecture simple and adaptable to machine choice Simplify system design CMOS sensors for the linear collider 50 mm 50 mm Readout direction 13 mm Red line: control electronics (sampling and readout). Minimal space. Red rectangle: readout electronics (column amplifiers + ADC + sparsifying circuit) Either on same substrate or bump-bonded to sensor substrate Ladder with 1 (2) sensor(s) Sensor size: 100 mm *13 mm, read out at both sides Number of pixels per sensor: 2500 x 650 In each pixel: 20 samples For ILC: sample at 50 ms during beam-on periods and store 20 samples in the pixel Column parallel readout between trains on multiple lines @ 1 MHz  a few ms read-out time

19. Seed 3x3 5x5 FAPS source test • Correlated Double Sampling readout (subtract Scell 1) • Correct remaining common mode and pedestal • Calculate random noise • Sigma of pedestal and common mode corrected output • Cluster definition • Signal >8 seed • Signal >2 next • Note hit in cell i also present in cell i+1. • S/Ncell between 14.7±0.4 and 17.0±0.3 J. Velthuis (Liv)

20. FAPS Hit resolution • Take hits found in cell 2 • Reconstruct x and y each cell using Centre-of-Gravity • Calculate average hit position • Determine residual position for each memory cell • Hit resolution approximately 1.3 m • Hit Resolutionspatial resolution!!! J. Velthuis (Liv)

21. FAPS efficiency estimate • Find hits in all cells • Plot max S/Npixel in 3x3 area around expected hit position if hit not found • Define: • Clearly, strongly dependent on seed cut. Lowering seed cut to 5 yields inefficiency ranging between 0.08±0.08% and 0.5±0.1% J. Velthuis (Liv)

22. MAPS plan Design: Phase 1: dedicated run with several test structure for FAPS: simulation and test results to analyse effects of storage cell size, numbers, read-out speed Phase 2: non-stitched 2 cm x 2 cm uniform sensor Phase 3: full size, stitched layer 1 sensor Mechanical mounting: CVD diamond Readout ASIC. ‘Alignment’ to CCD/ISIS readout  cost saving Explore possibility of sharing technology (ISIS, readout circuit)  cost saving.

23. MAPS under LCFI Groups involved: Liverpool, Glasgow, RAL-EID, RAL-PPD (?) 3 runs to XFAB ~ £200k ( Jazz025 ?) CVD diamond ~£40k PCB ~ £20k DAQ ~ £10k Design effort (RAL EID): about 3.8 SY. Cost  £250k (to be discussed within MI-3) Technician in Liverpool (50% over 5 years): £75k Some effort from RA already requested within LCFI RAs from rolling grants in Liverpool and Glasgow Total cost: ~£600-700k