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CDA 3101 Fall 2013 Introduction to Computer Organization. Division 30 September 2013. Review. Multiplication can be implemented using simple shift and add hardware Algorithm is similar to the grade-school method
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CDA 3101 Fall 2013Introduction to Computer Organization Division 30 September 2013
Review • Multiplication can be implemented using simple shift and add hardware • Algorithm is similar to the grade-school method • Booth’s algorithm for two’s complement • Handles all cases of positive/negative operands • More efficient than conventional algorithm 2n + 2n-1 + 2n-2 + … + 2k = 2n+1 - 2k • Further optimization is possible • MIPS multiply instructions ignore overflow • Multu: Hi = 0 • Mult: Hi = replicated sign of Lo
Division • Long division of unsigned binary integers 0 0 0 0 1 1 0 1 1 0 1 1 1 0 0 1 0 0 1 1 1 0 1 1 0 0 1 1 1 0 1 0 1 1 0 0 1 1 1 1 1 0 1 1 1 0 0 Quotient Dividend Divisor Partial remainders Remainder Dividend = Quotientx Divisor + Remainder
Unsigned Division M Divisor Q Dividend Count n, A 0 START Shift left: A, Q A A - M No Yes A < 0? Q0 0 A A + M Q0 1 Count Count - 1 No Yes Quotient in Q Remainder in A Count = 0 ? END
Division Hardware Divisor M31 . . . M0 32-bit ALU 4’ Add 2 Subtract 4’ write 0 Control 4 write 1 1 SLL 3 A31. . . A0 Q31. . . Q0 Dividend
Examples A Q 0000 0111 0000 1110 1101 1110 0000 1110 0001 1100 1110 1100 0001 1100 0011 1000 0000 1000 0000 1001 0001 0010 1110 0010 0001 0010 M = 0011 7 / 3 : Initial values Shift A = A - M A = A + M 1 Shift A = A - M A = A + M 2 Shift A = A - M Q0 = 1 3 Shift A = A - M A = A + M 4
Signed Division • Simplest solution • Negate the quotient if the signs of divisor and dividend disagree • Remainder and dividend must have the same signs • Remainder = (Dividend – Quotient * Divisor) (+7) / (+3): Q = 2; R = 1 (-7) / (+3): Q = -2; R = -1 (+7) / (-3): Q = -2; R = 1 (-7) / (-3): Q = 2; R = -1
Signed Division Algorithm A, Q Dividend M Divisor, Count n START Shift left: A, Q S A31, Count Count - 1 No Yes A A + M M31 = A31? A A - M No Yes S= A31? Yes No A=0 and Q=0 ? Q0 1 Restore A Quotient in Q Remainder in A Yes No Count = 0 ? END
Examples (1/2) A Q 0000 0111 0000 1110 1101 0000 1110 0001 1100 1110 0001 1100 0011 1000 0000 0000 1001 0001 0010 1110 0001 0010 A Q 0000 0111 0000 1110 1101 0000 1110 0001 1100 1110 0001 1100 0011 1000 0000 0000 1001 0001 0010 1110 0001 0010 M = 0011 M = 1101 Initial values Initial values Shift Subtract Restore Shift Add Restore 1 1 Shift Subtract Restore Shift Add Restore 2 2 Shift Subtract Q0 = 1 Shift Add Q0 = 1 3 3 Shift Subtract Restore Shift Add Restore 4 4 (7) / (3) (7) / (-3)
Examples (2/2) A Q 1111 1001 1111 0010 0010 1111 0010 1110 0100 0001 1110 0100 1100 1000 1111 1111 1001 1111 0010 0010 1111 0010 A Q 1111 1001 1111 0010 0010 1111 0010 1110 0100 0001 1110 0100 1100 1000 1111 1111 1001 1111 0010 0010 1111 0010 M = 0011 M = 1101 Initial values Initial values Shift Add Restore Shift Subtract Restore 1 1 Shift Add Restore Shift Subtract Restore 2 2 Shift Add Q0 = 1 Shift Subtract Q0 = 1 3 3 Shift Add Restore Shift Subtract Restore 4 4 (-7) / (3) (-7) / (-3)
MIPS • Multiply and divide use existing hardware • ALU and shifter • Extra hardware: 64-bit register able to SLL/SRA • Hi contains the remainder (mfhi) • Lo contains the quotient (mflo) • Instructions • Div: signed divide • Divu: unsigned divide • MIPS ignores overflow ? • Division by 0 must be checked in software
Registers 32 16 Sign extend 0 1 IR: M ALU Sub Control Unit Operation Zero Overflow 0 1 2 Memory address SLL/SRA Hi Lo MIPS Processor