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ASIC to FPGA Conversion Flow

ASIC to FPGA Conversion Flow. Special Functions Identification. RTL Code. Quick Conversion. Timing Specification. STA. ASIC Netlist. ATPG. Fault coverage. Testability report. Design Rules Checking. Design Rules Report. Pin-out when applicable. Check Die size. Check

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ASIC to FPGA Conversion Flow

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  1. ASIC to FPGA Conversion Flow

  2. Special Functions Identification RTL Code Quick Conversion Timing Specification STA ASIC Netlist ATPG Fault coverage Testability report Design Rules Checking Design Rules Report Pin-out when applicable Check Die size Check Bond Die / Package Feasibility Report Conversion Feasibility Flow Chart

  3. RTL code Behavioral code Timing specification Atmel gate level netlist Synthesis Design Rule Checks Design compiler (Synopsys) Star (in-house) Testability Insertion DFT Advisor (Mentor)- Scan BIST Architect (Mentor)- BIST BSD Architect (Mentor) – JTAG (only on used pads) Placement Formal Proof Clock Tree Synthesis Silicon Ensemble (Cadence) F.E. CTGEN (Cadence) Formality (Synopsys) Timing constraints STA Primetime (Synopsys) Delay Tuning no Routing Post-layout netlist Nano Route (Cadence) yes Customer test benches or VCD results SDF +Verilog / VHDL net list +ASIC Lib Logic Simulations Modelsim (Mentor) Simulation Comparison Simulations SIRAS (in-house) Atmel activity or data Customer activity or data Joint Atmel customer activity Tester rules check Sign off DRC/LVS TAPE OUT Conversion flow

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