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ECE 44 8 – FPGA and ASIC Design with VHDL

Lab 1 Introduction to Aldec Active HDL Implementing Combinational Logic in VHDL. ECE 44 8 – FPGA and ASIC Design with VHDL. George Mason University. Introduction to Aldec Active-HDL. Example 1 : MLU. MLU Block Diagram. Experiment 1 Problem 1 ALU of PIC Microcontroller.

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ECE 44 8 – FPGA and ASIC Design with VHDL

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  1. Lab 1 Introduction to Aldec Active HDL Implementing Combinational Logic in VHDL ECE 448 – FPGA and ASIC Design with VHDL George Mason University

  2. Introduction to Aldec Active-HDL Example 1: MLU

  3. MLU Block Diagram

  4. Experiment 1 Problem 1 ALU of PIC Microcontroller

  5. Pertinent Components of PIC W Working Register 7 0 Address 00000 7 0 00001 0 7 00010 7 0 STATUS 00011 7 0 8 Special Function Registers 00100 7 0 00101 7 0 Register File (32 Registers) 7 0 00110 7 0 00111 7 0 01000 24 General Purpose Registers 11111 7 0

  6. Addressing Modes Immediate mode W & 0x6C  W ANDLW H’6C’ Direct mode W & (0x12)  W ANDWF H’12’, 0

  7. Assembly language vs. Machine Code Assembly language mnemonic [operands] ANDWF H’12’, 0 ANDLW H’6C’ Machine code opcode [operands] ‘000101’ ‘010010’ ‘1110’ ‘01101100’

  8. Status Register STATUS 7 0 Z DC C Carry/Borrow Digit Carry (3rd4th bit) Zero Power-down Time-out Program Page Preselect Reserved

  9. Definition of the Status Register Flags (1) Zero flag - Z zero result Z = 1 if result = 0 0 otherwise Carry flag - C out-of-range for unsigned numbers C = 1 if result > MAX_UNSIGNED or result < 0 0 otherwise where MAX_UNSIGNED = 28-1 for 8-bit results

  10. Definition of the Status Register Flags (2) Carry / Borrow between MSB of first hex digit and LSB of second Digit Carry flag – DC DC = 1 if carry from bit 3 to bit 4 (ADDWF) or no borrow from bit 4 to 3 (SUBWF) 0 otherwise DC = 1 111 1 0010 0110 + 0001 1100 0100 0010 0010 1110 - 0001 1100 0001 0010

  11. Logic Instructions Z C DC • AND • ANDWFW & RF  W or RF • ANDLWW & L  W • 2. Inclusive OR • IORWFW | RF  W or RF • IORLWW | L  W • 3. Exclusive OR • XORWF W  RF  W or RF • XORLW W  L  W • Ones Complement • COMF RF  RF – – DIR IMM – – DIR IMM – – DIR IMM – – DIR

  12. Arithmetic Instructions Z C DC • 1. Addition • ADDWF W + RF  W or RF • Subtraction • SUBWF RF – W  W or RF DIR DIR • Increment • INCF RF + 1  RF • Decrement • DECF RF - 1  RF – – DIR DIR – –

  13. Shifts and Rotation Instructions Z C DC 1. Rotate Left Through Carry RLF 2. Rotate Right Through Carry RRF 3. Swap Nibbles SWAPF RF [7:4]  W [3:0] or RF [3:0] RF [4:0]  W [7:4] or RF [7:4] – – DIR x . . . C 7 0 – – x DIR . . . 0 7 C DIR – – –

  14. Instruction Summary

  15. Example 2 Mini ALU

  16. opcode 4 4 A 4 Mini ALU 4 R B 4 M

  17. Block diagram

  18. Example 3 Variable Rotator

  19. Function C = A <<< B A – 4-bit data input B – 2-bit rotation amount

  20. Interface A 4 2 B 4 C

  21. Block diagram C

  22. A(1) A(0) Fixed Shifts in VHDL A>>1 A(3) A(2) ‘0’ ‘0’ A(3) A(2) A(1) A_shiftR <= ‘0’ & A(3 downto 1);

  23. Arithmetic Functions in VHDL (1) To use arithmetic operations involving std_logic_vectors you need to include the following library packages: library ieee; use ieee.std_logic_1164.all; use ieee.STD_LOGIC_UNSIGNED.ALL;

  24. Arithmetic Functions in VHDL (2) You can use standard +, - operators to perform addition and subtraction: signal A : STD_LOGIC_VECTOR(3 downto 0); signal B : STD_LOGIC_VECTOR(3 downto 0); signal C : STD_LOGIC_VECTOR(3 downto 0); …… C<= A + B;

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