1 / 23

Improved Boundary Scan Design (Based on a paper by Lee Whetsel, Texas Instruments Inc.)

Improved Boundary Scan Design (Based on a paper by Lee Whetsel, Texas Instruments Inc.). Introduction. In a situation of which the circuit complexity increases, and no direct access for all places on the board is possible, the use of BS is a good alternative.

orde
Download Presentation

Improved Boundary Scan Design (Based on a paper by Lee Whetsel, Texas Instruments Inc.)

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Improved Boundary Scan Design (Based on a paper by Lee Whetsel, Texas Instruments Inc.)

  2. Introduction • In a situation of which the circuit complexity increases, and no direct access for all places on the board is possible, the use of BS is a good alternative. • There are many advantages of using BS for testing purposes.

  3. The problem: Two possible drawbacks concerning the use of BS: • Additional space is needed for the BS cells. • Signaling delay due to additional circuit components.

  4. The proposed solution: An innovative method of improving the design of the BS cells. • The method is based on the reuse of functional input/output buffers already in the circuit. • The method is compliant with IEEE 1149.1.

  5. Advantages of the method: The results of the method: • Reduced cell size. • Reduced signaling delay. • Improved test functionality.

  6. The Method

  7. Traditional 1149.1-2-state output BSC:

  8. Traditional 1149.1-2-state output BSC: Normal operation: Test operation: For self test

  9. improved 2-state output BSC Implement Mux2 Implements Mem2

  10. improved 2-state output BSC Cont. Normal operation: closed opened Test control signals

  11. improved 2-state output BSC Cont. New feature: Test operation: opened Closed after each Capture/shift Observability of output pin state (improve EXTEST operation and enables pin observation via scan during production testing)

  12. Comparing the two designs: • Reduction in BSC circuitry of approximately 40% over the standard BS 2-state output cell. If S1 and S2 are implemented in the buffer region with the LOB a reduction of about 50% will be achieved. • Improved performance – if S1 implemented as high performance transmission gate, the prop. delay through S1 to LOB is less than that of a core resident Mux2 driving a normal output buffer.

  13. Traditional IEEE 1149.1 3-state output BSC Test operation: Normal operation:

  14. Improved 3-State Output BSC Used in test mode (to maintain updated test data to the control input of the 3SOB) 2-state output BSC

  15. Improved 3-State Output BSC Test operation: Normal Operation: closed Can capture and shift data opened

  16. Comparing the two designs: The reduction in BSC circuitry is slightly less than before since the BH is added. We still get a reduction in the range of approximately 35% - 45%

  17. Traditional IEEE 1149.1 Input BSC Adds test circuitry and delays the input signal

  18. Improved input BSC Test operation: Important advantage: Normal operation: closed opened opened Direct access No need for hi-drive buffer Less space and signal delay

  19. Comparing the two designs: Since there is no need for hi-drive buffer in the improved design, the expected reduction in circuitry is approximately 45% - 55%.

  20. Improved Input/Output BSC

  21. Comparing the two designs: • The input/output BSC improved design gives the best opportunity to reduce overhead circuitry, since BSCs for input, output and control are involved. • The reduction in the cell size is by three Mux2s, three Mem2s and a hi-drive buffer per I/O pin or approximately 45% - 55%.

  22. TAPController of Improved BSCs

  23. Conclusion: The method described here has the following features: • It gives the opportunity to reduce circuitry of BSCs by up to one halfby reuse of functional input and output buffers. • It reduces signaling delays due to the use of S1.

More Related