Low Power, Multi-Gigabit DRAM Cell Design Issues Using SOI Technology

1. Low Power, Multi-Gigabit DRAM Cell Design Issues Using SOI Technology Fred Chen & Lixin Su May 12, 1999 A Presentation for EE241 Term Project Department of Electrical Engineering and Computer Sciences University of California at Berkeley

2. Outline of the Project • Background Study • SOI Technology • Low Power DRAM Design • DRAM Conceptual Design Using SOI • Spice3 for SOI Simulation • Simulations/Results/Conclusions • Summary and Future Work

3. SOI Technology for DRAM Vg Vs Vd Gate Tox Depletion Source Drain Tsi Body Vp Vb Tbox Vbg Substrate Fully Depleted (FD) Partially Depleted (PD) Dynamically Depleted (DD)

4. Low Power Small channel leak for same drivability (1) Junction leak reduction (3) Charge/discharge current reduction (2) Body control current reduction (6) Low Voltage High drive capability for same leak (1) Large cell readout signal (2) High speed operation (2) (4) Large high-data write margin (4) Easy to apply body control (5) SOI Technology for DRAM Related SOI Features (1) Small S-factor (4) Small substrate bias effect (2) Small Junction Cap. (5) Complete body isolation (3) Small Junction Area (6) Small Body Cap. Source: Shimomura et al., JSSC vol. 32, No. 11, Nov. 1997

5. SOI Technology for DRAM What Else? There’s more? : • Reduced Second Order Effects • Radiation hardened: Almost Soft Error Free • Cs reduced AREAreduced • Free from latchup • Disadvantages: • Floating body effect • Self-heating effect • Solution: • Body control through body contact schemes • Fully depleted SOI

6. Spice3 for SOI Simulation • Source:UC Berkeley Device Group • Versions: BSIMPD2.0 & BSIMPD2.0.1 & BSIMFD2.0 & BSIMDD2.0 BSIM3SOI1.3 • Model Card:{PD,DD,FD} x {PMOS, NMOS} • Spice3 Limitations: • Restricted .subckt & !.param => ! Sweep/Change MOS Parameter • !.measure => Extra Data Processing • Need to Improve Work Efficiency!

7. Parameters Model Card Perl Script Switch Spice Deck Spice PD DD FD Spice 3 Simulation Engine Results Spice3 for SOI Simulation • Simulation Flow:

8. Single Transistor SOI: The S-Factor

9. Single Transistor SOI: The S-Factor

10. Single Transistor SOI: The Kink

11. Single Transistor SOI: Pass Gate Leakage Current 0v ??? 1.5v 1.5v 0v

12. Low Power DRAM Design • Typical large scale low power architectures • Multi-divided data lines • Shared sense amplifiers • Divided word lines • Reduce CB, reduce CB! • Half-Vdd pre-charge • Boosted sense ground • SOI

13. Technology Comparison Use identical architectures Match relative performance of each technology model Use single cell comparison (with SA) Compare DRAM metrics for each technology DRAM: Comparison Scheme

14. Dummy Cell DRAM SOI: Cell & Sense Amplifier WL Cell D W p r Vdd/2 a Wr Wbar Dbar

15. Read/Restore Write 0 Write 1 wl phia phir wr w wbar DRAM SOI: Control Signals phip

16. DRAM SOI: Bit-Line Capacitance

17. Simulation Results

18. Round 1: Bulk vs. SOI

19. Round 2: PD vs. FD

20. Conclusions Performance: FD PD-ActB PD-FltB PD-FixB High Low Power: FD PD-FixB PD-FltB PD-ActB Low High

21. PD vs. FD Tradeoffs • Which to choose for DRAM? • Fully Depleted SOI • Pros: Low Power, Low CJ, low S-factor, no body contact needed, less sensitive to temperature variation • Cons: Manufacturability, sensitivity to process variation • Partially Depleted (floating body) • Pros: Easy to manufacture • Cons: Floating body • Inside PD: body contact tradeoffs, see last slide

22. Work Done & Future Work • Work Done: • Single transistor characterization for SOI • Comparison between bulk/different SOI body contact schemes for DRAM cell design • Future Work: • More SOI simulation of each component of DRAM • More SOI simulation to study coupling effect, standby current, & pass gate leakage current • Voltage scaling & transistor sizing with SOI