BlueArch Update

1. BlueArch Update

2. Updated List of Topics • M1: Combinational Circuits • M2a: Sequential Circuits • M2b: Pipelined Circuits • M3: Memories • M4: MIPS ISA • M5: Single-Cycle Processor with Magic Memory • M6a: Princeton Architecture • M6b: RAW Hazards • M7: Realistic Memory Model • M8: Caches • M9: 5-stage Processor Pipeline • M10: Exceptions • M11: Advanced Topics

3. M1: Combinational Circuits • adders • ripple carry adder • carry look ahead adder • multiplier • shifters • multiplexer • logic unit • ALU

4. M2a: Sequential Circuits • flip flops • register files • counters • multi-cycle combinational circuits • adders • multipliers • dividers

5. M2b: Pipelined Circuits • pipelined circuits without hazards • adders • multipliers • dividers

6. M3: Memories • ROM • SRAM • DRAM • Magic (Combinational) • Realistic (variable latency)

7. M5: Single-Cycle Processor with Magic Memory Instruction Fetch Decode Execute Writeback ALU Branch Ld/St 2-port Magic Memory

8. M6a: Two-Cycle Processor with Magic Memory Instruction Fetch Decode Execute Writeback ALU Branch Ld/St 2-port Magic Memory

9. M6a:Branch Resolution, Instruction Kill Instruction Fetch Decode Execute Writeback ALU Branch Ld/St 2-port Magic Memory

10. M6a: Princeton Architecture Memory Writeback Reg Write Instruction Fetch Decode Reg Read Execute Branch ALU Ld/St 1-port Magic Memory

11. M6a: 3-Stage Harvard Memory Writeback Reg Write Instruction Fetch Decode Reg Read Execute Branch ALU Ld/St 1-port Magic Memory

12. M6b: RAW Hazard Instruction Fetch Decode Execute Writeback ALU Branch Ld/St 1-port Magic Memory

13. M7: Realistic Memory Instruction Request Inst Resp, Decode Execute Ld/St Response Writeback ALU Branch Ld/St Req Realistic Memory

14. M8: Caches Instruction Request Inst Resp, Decode Execute Ld/St Response Writeback ALU Branch Ld/St Req ICache DCache Realistic Memory

15. Cycle Counts