Project Stickleback A CMOS Weekend Countdown Timer

1. Project SticklebackA CMOS Weekend Countdown Timer • Advisor • Joseph P. Hoffbeck, Ph.D. • Yuin-Hwa Lu, Ph.D. • Industry Representative • Mr. Chris Vondrachek • Intel Corp. Authors Tony Faris Joe Leineweber Jeff Schlichting University of Portland School of Engineering

2. Agenda • Introduction Jeff • Background Jeff • Methods Tony • Results Tony • Conclusions Joe • Demonstration Joe University of Portland School of Engineering

3. Introduction • Thank you’s • Advisors • Dr. Hoffbeck • Dr. Lu • Informal Advisors • Dr. Osterberg • Sandy Ressel • Rick Severs • Industry representative • Chris Vondrachek University of Portland School of Engineering

4. Introduction • Problem • Determine the amount of time remaining in the workweek • Solution • Project Stickleback – A CMOS Weekend Countdown Timer University of Portland School of Engineering

5. Introduction • What time does it use? • 9am Monday for the week start • 5pm Friday for the week end • What does it display? • Displays the days, hours, minutes, and seconds left in the work week • Displays a separate message on the weekend University of Portland School of Engineering

6. Background • Key Features • Visibly display the remaining time in the workweek • Run without supervision • Allow users to easily set the time University of Portland School of Engineering

7. Methods • Fall 2003 • Hand design • B2Logic simulation • .tpr file • MOSIS fabrication University of Portland School of Engineering

8. Methods • Spring 2004 • Macromodel – Verilog file • System construction • MOSIS chip replacement and finalization University of Portland School of Engineering

9. Results University of Portland School of Engineering

10. Results • MOSIS chip B2Logic simulation University of Portland School of Engineering

11. Results University of Portland School of Engineering

12. Results University of Portland School of Engineering

13. Results • .tpr file University of Portland School of Engineering

14. Results • MOSIS chip layout University of Portland School of Engineering

15. Results • Verilog file University of Portland School of Engineering

16. Results University of Portland School of Engineering

17. Results University of Portland School of Engineering

18. Conclusions • System 100% Verified • All Tasks Completed On-Time • All Objectives Were Successfully Met • Designed and fabricated a CMOS chip • Took an idea all the way to a product • Learned how to work in a team environment University of Portland School of Engineering

19. Demonstration:Setting the Clock University of Portland School of Engineering

20. Demonstration:Monday Morning University of Portland School of Engineering

21. Demonstration:Monday Morning University of Portland School of Engineering

22. Demonstration:Friday Evening University of Portland School of Engineering

23. Demonstration:Friday Evening University of Portland School of Engineering

24. Questions? University of Portland School of Engineering