Capture Analyze Simulate

Capture Analyze Simulate

TimeWizTMAn Integrated Design Environment for Real-Time Systems TimeWiz is a unique and powerful product that lets you represent hardware and software, analyze and simulate the timing behavior of your system, model processors and networks for end-to-end performance, chart your system parameters and generate integrated system reports. All nicely integrated and affordable.

Recommended Introduction to TimeWizTM Solving Your Problems See how TimeWiz addresses problems specific to your application context. TimeWiz: A Quick Tour Take a quick whirl-wind tour of TimeWiz. TimeWiz Architecture Check out the flexible TimeWiz framework, and the powerful, standard system model. Key User Interface Features Check out the latest and finest user interface under Windows. Application Domains Find out various application domains where TimeWiz can be effectively applied. Please click on an icon of interest Exit Presentation

Your problems addressed by TimeWiz Please click on an icon of interest RMA based single node analysis Analyze your single processor system to estimate the worst- case timing behavior with Rate-Monotonic, Deadline-Monotonic or any other Fixed-Priority scheduling scheme, used universally by real-time operating systems. CanBusAnalyze the worst-case response times of all CANbus messages based on their message IDs, sizes and frequencies. Use in your distributed system and analyze/simulate end-to-end response times. Multiple Resource Constraints Map software elements to hardware resources automatically to satisfy multiple resource constraints (processing times, memory requirements, bandwidth requirements, logical sharing) simultaneously. See the damaging effects of priority inversion and use a priority inheritance protocol to take control. Networks (Ethernet/FDDI) Study the effect of collisions, visualize deterministic Vs. non-deterministic utilization. Model your own custom protocols(e.g., token passing/TDM) on top of the standard models. Distributed Systems Represent your large system exactly as comprising of multiple processing elements and network links. Analyze the worst-case end-to-end latencies encountered by your data streams. Simulate to obtain the stochastic distribution of the end-to-end latencies. Network elements are included in both analysis and simulation. Interactive Reconfiguration Represent your hardware and software architectures independently and hierarchically. Then use a hybrid of automatic algorithms and manual assignments to bind software elements to hardware, updating numbers on the fly. Response to External Events Trace paths of responses to external events through yourhierarchical, distributed system of processors and networks. Analyze and simulate to find worst-case and average case times. Simulation A powerful simulation engine models your processes, whether processor or network based. Specify stochastic arrivals and/or executions; obtain statistical distribution of response times. Go back to Introduction to TimeWiz

Problem Significance • Timing constraints (deadlines) can be violated even at very low utilization levels. • Missed deadlines may be annoying or result in loss of revenue and/or lives. • Planning up-front saves significant effort during integration, testing and certification processes. • Extended periods of testing and simulation may not identify all scenarios. • The “Mars Pathfinder” had timing (priority inversion) problems on Mars and was fixed from Earth using RMA techniques. • Explicit resource management techniques must be applied in systems with multiple processes, priorities and shared resources.

TimeWiz Solution • Mathematical framework computes the worst-case timing possible under all possible combinations • Rate-Monotonic Analysis (RMA) • Support for real-time scheduling policies • Rate-monotonic, deadline monotonic, fixed priority, etc. • supported by most (if not all) real-time operating systems • Support for synchronization (data sharing) policies • priority inheritance protocols that control priority inversion: • basic priority inheritance protocol, priority ceiling protocol, highest locker priority protocol, etc. • FIFO (no control) • Compute preemption time, blocking time and completion time • Support for triggered sequences of actions, each with own priority • What-if analysis

Rate-Monotonic Analysis • Use of Software EngineeringInstitute (SEI) standard model • Resources represent hardware • Events represent triggers • Actions represent executable code or messages • Compute schedulability using RMA • Incorporate context switch time • Associate scheduling and data sharing policies with Resources • Define objects, properties and default values, which can then be changed per-instance basis

Binding and Results • Associate arrival patterns (e.g., period) with events • Define priorities and execution times for actions • Bind actions to resources, manually and/or automatically(to satisfy multiple constraints simultaneously) • TimeWiz instantly computes the worst-case completion times • Visualize a detailed “Timeline” viewwith preemptions, blocking etc.

Stochastic Modeling • Define distributions for arrivals, execution times etc. • Choose from a wide variety of statistical distributions(normal, uniform, exponential, beta, gamma, cauchy…) • Obtain minimum, maximum, average and standard deviations of completion times, end-to-end response times, etc. • Set the simulation span and visualize details using the Timeline view • Enable traces to view even more details

Problem Significance • Priority Inversion can occur when using shared resources • Making critical sections smaller reduces the probability; the possibility still exists • Possibility of deadlocks not eliminated even with Priority Inheritance protocol • Performance penalty exists with various protocols • Use of adequate protocol provides trade-off between performance and missed deadlines Priority Inversion causes the high priority task to miss deadline.Figure at the bottom uses Priority Inheritanceto avoid the problem.

TimeWiz Solution • Analyze, simulate and visualize the behavior of multiple data sharing protocols • Associate multiple logical resourceswith a single physical resource • Specify logical resource requirements for each action • Automatically calculate completion times for all tasks • Visualize the execution timeline with specified arrival times You can write your own custom analysis and simulation plug-ins to model custom policies and network elements in your system.

Data Sharing Policies (1) • FIFO (First-In-First-Out) - Static priorities, first task to request a logical resource can lock it. • Can lead to unbounded priority inversion and cause weird timing problems at different times. • Basic Priority Inheritance Protocol - When an arriving higher priority task finds a lower priority task holding a lock it wants, the lower priority task inherits the priority of the higher priority task (until the lock is released). • Priority inversion is (normally) bounded but still can be long. • Interrupt Masking - Disable interrupts (and/or preemption) when a shared resource is locked. • Priority inversion is bounded but can be unacceptably long.

Data Sharing Policies (2) • Highest Locker Priority Protocol - On locking a shared resource, a task executes at the highest priority of all tasks that can lock the shared resource. (This highest priority is called the “priority ceiling” of that shared resource). • Priority Ceiling Protocol - A task can lock a shared resource only if its priority is strictly greater than the priority ceilings of all shared resources locked by other tasks. • Both the highest locker and priority ceiling protocols bound priority inversion to the duration of at most one critical section. • This behavior can be much better than (and at worst the same as) that of the basic priority inheritance protocol.

Timeline View • Customize arrivals, end times • Enable/disable display of labels • task ready • task start • task end • task preempted • task blocked • task locking logical resource • task unlocking logical resource • Zoom by percent or by region • Pan using an Overview window • Different colors for each task

Problem Significance • Complex hardware and software architecture • Mapping functionality to hardware during the design and maintenance without violating constraints of processing/ memory/ bandwidth etc. • External events and system response to them need to be represented/ analyzed/ simulated • Accurate modeling of each element (processors, networks, protocols) is required for realistic results • Existence of several instances of same type of components (each is uniquely named)

TimeWiz Solution • Hierarchical representation withconnectivity propagation viaInter-Diagram Connectors • Independent hardware and software hierarchies • Interactively bind software to hardware and immediately view violations of processing/bandwidth constraints • Use Tracers to represent end-to-end timing constraints and automatically calculate worst-case and average-case response to external events • Analyze and simulate every element in your system using standard TimeWiz modules or build your own using an easy-to-use Application Programming Interface (API) • Catalog, extend and re-use objects, properties and models. Inter-Diagram Connectors

Hierarchical Representation • Use the powerful diagramming engine to represent your hierarchical system • Visual navigation of your hierarchy • Retain connectivity between objects when moving & resizing • Automatically propagate connectivity to multiple diagrams in the hierarchy • Collapse/un-collapse hierarchy to reduce/increase hierarchy levels • Set fonts, colors, line styles • Group, ungroup, align, abut • Zoom, pan, preview, print Collapse

End-to-end Timing • Define your software hierarchy using (periodic or aperiodic) execution Triggers and a sequence of Actions • Represent external events using Tracers and draw a path through system elements representing their processing • Inter-Diagram Connectors automatically keep track of connections spanning diagrams • RMA-based analysis automatically updates worst-case response • Use simulation to update average, min, max response

? Design Implementation Problem Significance • Simulation of computer systems often suffer from a lack of framework to support networks, custom protocols and components • After the initial estimates/assumptions and simulation, there is no method for refining the estimates based on implementation • In distributed system simulation, responses to external events are affected by resource (processing/ bandwidth) constraints, which must be taken into consideration. • In addition to standard data collection and visualization, flexible trace and debug mechanism are useful in viewing more details of the simulated session.

TimeWiz Solution • TimeWiz supports a powerful framework and a plug-in architecture for development of component models • Standard models for processors and networks (CANbus, Ethernet, FDDI, Serial) are supplied with TimeWiz • Statistical models derived from traces of an implemented system (e.g., VxWorks, pSoS, W/CE) can be incorporated directly • Simulation model supports distributed system response to external events (see External Events Tour) • TimeWiz supports a powerful debug, trace facility which can be extended via Basic scripting to support animation of visual objects. TimeWiz Online/OfflineSystem Trace Translator Importer

Simulation Model • Built-in process-oriented Simulation Engine with Event, Queuing, Scheduling, Pre-emption support • Simulation models execute as plug-ins of TimeWiz • Built-in models support CPUs(with standard scheduling anddata sharing policies) and networks(Ethernet, CanBus, Serial, FDDI) • Easy-to-use API (Application Programming Interface) for custommodel development • Fully integrated trace, debug andtimeline support TimeWiz User Interface Tracing and Debugging Simulation Engine Model Execution Support ModelInterfaceSupport Plug-in Models

System Trace Import • System trace (e.g., WindView) data can be fit to a statistical model and imported • Objects may be created or existing object properties may be updated • Provides a means to go from implementation to design • Standard import file format allows import from various file formats and plant databases Object event Trigger Temperature Monitor Property TWZPeriod 120.34 Object resource CPU Mission Computer Property TWZSpeed 23.45 Object action CPU MyAction Property TWZWorstExecutionTime 10.0 Property TWZResource Mission Computer Property TWZDistExecutionTime Normal,12,0.8 … Online/OfflineSystem Trace Translator TimeWiz

CAN Bus analysis • Guarantee transmission of all messages (highest priority and others) • Bus utilization • End-to-end timing • Response to external events

Problem Significance • Ethernet is not deterministic and therefore can only be simulated • Simulation should also consider processor loading • Metrics on collisions and utilization are needed in architecture design • Protocols implemented on top of Ethernet (e.g., token passing, time domain multiplexing) may allow deterministic response times • Custom analysis and simulation is needed for these protocols

TimeWiz Solution • A plug-in module is provided for Ethernet simulation • Collisions and utilizations of the networks is tracked and presented within TimeWiz Graphical User Interface • Completion time metrics for network transmission tasks is also tracked and presented via TimeWiz GUI • Source code for this plug-in provided on request to ease development of custom protocols • TimeWiz Catalog Designer can be used to define properties (e.g., TDM Size) for custom protocol development • TimeWiz API (Application Programming Interface) can be used to extend the analysis and simulation plug-in • get/set interface and event notification provided in the API for the custom properties defined in the Catalog Designer

TimeWiz Catalog designer Mandatory properties are automaticallycopied to other objects of same “Type”,supporting the concept of inheritance Support for various data types, includingnumeric, strings, enumerate, object referencesand lists of objects Group objects into palette and palettesinto catalogs. Merge, import and exportcatalogs to/from projects, thus adding properties to an existing project A set of properties AND avisual symbol can be associated with a custom object Full control over where (inspector, tables, plots, reports), in which order, and which format to display each property of each object within TimeWiz GUI

Application Programming Interface • Simple and powerful; work in conjunction with catalog designer • Analysis modules get called when • values change (for validity checking, updating) • analysis or simulation runs • what-if analysis • object creation and destruction • automatic binding • initialization, termination • Uniform object interface provided for • get/set values • overloaded functions for different prototypes • callback support • message outputs

Problem Significance • No Real-Time analysis tools available to track resource constraints including processing and bandwidth usage • Dynamic reconfiguration of functionality to hardware results in new resource usage patterns and analysis needs to be repeated • For systems with large number of standard components, automatic binding based upon resource constraints is highly useful • Automatic binding needs to support needs of some software elements that can only run on specific hardware

TimeWiz Solution • Define hardware hierarchy • Define software hierarchy • Bind software elements to hardware • Watch as resource constraints are updated and completions based on the constraints are also updated • Use bin-packing and/or load-balancing algorithms for automatic binding • Use a combination of manual and automatic binding • Change the binding anytime and watch the numbers updated

Multibus Box + Multibus Box - Processors + Multibus Box - ADC Ports i386 CPU Processors - CPU Communications Hierarchical Hardware Definition Multibus i386 Network i386 SBC Comm. Processor

Monitor + Monitor - M_Threads + Event E1? Event E3? Read_State Read_Info Process_Data Process_Info Output_Message Output_Message Trigger E3 Trigger E2 Hierarchical Software Definition Temp Monitor E1 E2 Alert Communications E2 Temperature Alert E1 Monitor - M_Threads - M_Actions

Multibus Box - Processors - CPU Communications Monitor - Event E1? Event E3? Read_State Read_Info M_Threads - Process_Data Process_Info M_Actions Output_Message Output_Message Trigger E3 Trigger E2 Binding Software to Hardware ADC Ports i386 CPU Drag-and- drop Both manual and automatic binding are supported.

12 12 10 4 6 3 8 11 9 9 10 8 2 2 3 6 5 4 7 5 11 7 1 1 Automatic Binding of S/W to H/W • bin-packing: • leave capacity for future growth • have processors “idle” for replication of critical tasks • we apply “best-fit” bin-packing • load-balancing: • spreads out tasks so that some task is likely to get hurt if any node fails. Bin-packing Load-balancing

Historical Archives Operator Stations Protection Functions High Speed Network Gateway Logging & Printers Control Functions Field (Process) Problem Significance • The functionality to handle an external event is typically ‘distributed’ across multiple processors and/or networks • Each external event handled by a different path through the system • When mapping of functionality to hardware element(s) change, response requirements should still be satisfied • Worst-case response times to external are needed for system certification for operation in safety-critical systems • Worst-case is often too pessimistic; average response time is more useful for comparison of vendors and architectures Update Display on High Temperature High Temperature Event

TimeWiz Solution • Diagram your hardware and software hierarchy independently • Draw the path of external events via Tracersthat travel through software hierarchy • Use ‘glued’ connectors and propagate connectivity across the entire software hierarchy • Rate-Monotonic Analysis (RMA) based analysis automatically updates worst-case response time, if possible. • Perform a comprehensive simulation with accurate component models to obtain minimum, maximum, mean and standard deviation of system response to each Tracer. • Interactively change the binding of software elements to hardware and watch the numbers updated! Transmit Data Process Input Update Display High Temperature Event

Tracers • Define arrival patterns for tracers via property inspector or table • Define execution patterns for actions • Define tracer path diagrammatically orusing property inspector or table • Perform analysis to update worst-case response • Perform simulation to update statistical response

A Whirlwind Tour of TimeWiz • In this section, you will learn how TimeWiz can be used to represent, analyze, simulate, plot and document your real-time system. • Define your system visually and easily using catalogs and palettes, • Represent hierarchically both the hardware and software configurations of your system, • Use multiple views to and hierarchical representation, • Run Timing Analysis and Simulation, and interpret the results, • Visualize results using multiple plot types, • Document your system with multiple integrated views, • Customize pretty much every aspect of TimeWiz, and • Exploit TimeWiz’ knowledge of commercial real-time OSs.

Catalogs • A “catalog” file (with extension “.twc”) is associated with every TimeWiz project. • This file contains a set of resource objects, event objects, action objects and logical resource objects. • Objects are grouped into palettes • Each object has a visual symbol with pre-defined attributes (such as Name) whose associated values can be modified/read within TimeWiz.

Using Catalogs • TimeWiz comes with many catalogs that you can use readily. • You can derive/create new catalogs using the TimeWiz Catalog Editor. • you can create new objects, edit visual symbols and add new attributes. • You can also contact TimeSys Corporation (at info@timesys.com) to derive/create custom catalogs to satisfy any special needs.

Represent Hardware Architecture • You can represent your hardware architecture visually and hierarchically using resource palettes defined in various catalogs

Using Palettes • Palettes are collections TimeWiz objects • They are part of TimeWiz catalogs • Use default palettes or create/modify palettes to suit your own needs • Three types of palettes: Resource, Action and Event Palettes

Hierarchical Representation • You can capture your hardware architecture in a hierarchical manner • Hierarchy browser helps you to navigate to different levels of the hardware architecture

Capture Analyze Simulate

Capture Analyze Simulate

Presentation Transcript

analyze

Using Wireshark to Capture and Analyze Network Data

ANALYZE

USING WIRESHARK TO CAPTURE AND ANALYZE NETWORK DATA

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Simulate Multiple Dice

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RSA3408A Trigger, Capture, Analyze!

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Simulate to Stimulate

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Aim: Capture and simulate memCtrlr element