Solar Energetic Particle instrument Front end/sensor Pre-PDR peer review

1. Solar Energetic Particle instrumentFront end/sensor Pre-PDR peer review Davin Larson, Rob Lillis, Ken Hatch, David Glaser David Curtis UCB

2. Foil Detector Al/Polyamide/Al Foil (stops ions <350 keV?) Thick Detector Open Detector Electrons Ions Foil Collimator Open Collimator Attenuator Attenuator Sm-Co Magnet (sweeps away electrons <350 keV) SEP instrument overview • The Solar Energetic Particle (SEP) instrument measures the energy spectrum and angular distribution of solar energetic electrons (30keV–1 MeV) and ions (30 keV-12 MeV).

3. Sensor Units • Each sensor unit is a: • Dual-double ended solid state telescope • Each double ended telescope (1/2 sensor) has: • Triplet stack of silicon solid state detectors • Foil (on one side) • Filters out ions <~200 keV? • Leaves electron flux > ~20 keV nearly unchanged • Magnet / Open side • Filters out electrons <350 keV • Leaves ion flux nearly unchanged • Mechanical Pinhole attenuator • Reduces count rate during periods of high flux • Reduces radiation damage (caused by low energy ions) during periods of high flux • Collimators • Preamplifier / shaping electronics

4. Sensor Cross Section Foil Collimator Attenuator Foil Detector Stack Magnet Attenuator Open Collimator

5. Location of SEP Sensors and Fields of view (FOVs). APP REVISED SEP FOVS

6. APP Sweep Volume PLENTY OF CLEARANCE TO ACCOUNT FOR REQUIRED APP SWEEP VOLUME CHANGES NEW SEP FOVS APP SWEEP VOLUME APP SWEEP VOLUME MUST BE INCREASED SOME TO ACCOUNT FOR CHANGES FROM IUVS AND STATIC

7. Changes from THEMIS SST Sensor design • Foil is closer to detector stack: 0.73 cm → 0.19 cm. • Higher % of electrons scattering in foil reach detector. • Foil thickness may decrease from 4.3 µm to 2 µm. • Detection of electrons down to ~20-25 keV (previously 30 keV). • Allows better cross calibration with SWEA and SWIA. • Increased geometric factor: 0.1 → 0.155 cm² sr • Detector area is 17% bigger: 0.92 cm² → 1.08 cm² • FOV has expanded from 40° x 23° to 40° x 31.5° • Detector casing was formerly PEEK, now brass. • Better radiation protection.

8. Moving foil closer to detector. Rationale: electrons scatter in the foil & can miss detector. CASINO simulations

9. Foil thickness is a science trade-off • We would like to extend our energy range as low as possible for greater overlap with SWIA and SWEA. • What are the consequences of thinner foils? • Pro: buys several keV. • Con: lower energy protons penetrate

10. Electron transmission through foils:

11. Proton energy loss in foil depends on thickness

12. Proton energy loss in foil

13. Expected fluxes & SEP detector count rates • Without attenuation, protons may saturate the detector during the very largest events. • Below are representative spectra and count rates.

14. Changes from THEMIS SST Electronics design Electronics is now on 2 boards (instead of one) Each board is independent with 6 channels (one sensor) Separate bias supplies - FPGAs Switch preamplifier from Amptek 225FB to 250F (eliminate “obsolete” part, power is a wash, eliminate undesirable current surge at power on, improves performance considerably) New pulse shaping chain (similar characteristics -2.5 us) Comparator change (MAX907 to AD8561) Separate test pulsers for each chain. (Allows testing for cross talk) Add ADC for analog housekeeping. Add 3.3 Volt digital line to reduce power. Switch diodes in bias supply. No longer sensing attenuator position. Switch to dual MDM connectors on DFE No more internal thermostat or internal heater Adding Burst capability to FPGA

15. SEP Detector Stack Assembly DFE Board Subassembly BeCu Gasket (3) Detectors (4) KaptonHeater Spring Clamp PEEK Spacer (4) Spring Plate (2) Kapton Flex-Circuit (4) AMPTEK Shield Thermostat Detector Board Composition (exploded view)

16. Electronics Block Diagram • Signal chain: 1 of 12 channels shown Bias Voltage Test Pulser DAC Gain + shaping Thresh FPGA Coincidence Logic & Accumulators PD A250F Preamp Shaper ADC Memory BLR DFE Board DAP Board

17. THEMIS SST preamp design • Using Amptek 225FB (6pin sip Hybrid - special request) • Characteristics: • ~6 keV electronic noise (with 1.5 cm2 detector) • ~2.5 uS shaping time (time to peak) • ~26 mW (Increases with negative supply voltage) • 100 Krad (still needs ~3mm Cu shield) • Operating range: -55 to +125 C • Dual supply allows negative output pulses B

18. Preamp design changes for MAVEN SEP • Using Amptek 250F (6pin sip Hybrid) • Characteristics: • ~2 keV electronic noise (with 40 pF detector) • ~2.5 uS shaping time (time to peak) • 100 Krad (still needs ~3mm Cu shield) • Operating range: -55 to +125 C • Dual supply allows negative output pulses • Different pinout!

19. Detector Pixelation • Detectors similar to STEREO/STE • Produced at LBNL/Craig Tindall PI Active area 7 mm Guard ring 13.2 mm THEMIS SST & MAVEN EM

20. Detector Pixelation • Detectors similar to STEREO/STE • Produced at LBNL/Craig Tindall PI Active area 8.2 mm Guard ring 13.2 mm Additional Pixels not used for MAVEN MAVEN SEP

21. -35 V THEMIS SST Design ~200 A Polysilicon +4.5 V F n F Out p 225FB -2.5 V Pixelated side ~1200 A Dead layer F Test in p n T T Out 225FB n p T Test in O p O Out 225FB n Outside Grounded O Test in ~200 A Polysilicon + ~200 A Al 300 micron thick detectors

22. MAVEN SEP Design -35 V ~200 A Polysilicon +5 V F n F Out p 250F -5 V Pixelated side ~1200 A Dead layer F Test in p n T T Out 250F n p T Test in O p O Out 250F n Outside Grounded O Test in ~200 A Polysilicon + ~200 A Al Protection Diodes Added too 300 micron thick detectors

23. Sun in FOV for SEP • SEP FOVs • 2 SEP sensors with 4 apertures per sensor (only 2 of 4 apertures on each sensor are light sensitive) • 1 actuator closes all 4 apertures • Constraints on commands to SunSafe SEP • Takes ~ 200-500 ms (Temperature dependent) to close doors • SEP actuator must wait 15 seconds before it is re-actuated • SEP uses a status switch • Spacecraft needs positive confirmation of safing • Cannot damage SEP by sending multiple commands • Current actuator life tested to 70,000 cycles • Need to evaluate if this will be sufficient • SEP requires power to close actuators

24. DFE (Detector Front End)

25. Top Level

27. Pole zero/shaping

28. Level I requirement: • MAVEN shall determine solar energetic particles (SEP) characteristics, 50 keV to 5 MeV protons, with ~1 hr resolution characteristics of SEP events. Requires energy resolution better than 50%; accuracy better than 30%. • Rationale: • SEPs precipitating into the martian atmosphere provide energy input that contributes to controlling upper-atmospheric processes, and may provide a direct driver of loss of atmosphere to space.

29. Digital Boards • Digital/FPGA portion of SEP DAP board

30. FPGA/Digital Design- • The MAVEN/SEP FPGA Design is based on the THEMIS/SST FPGA Design. Only minor changes are required: • THEMIS design had 12 channels/board – MAVEN/SEP will have only 6 channels. (2 boards) • MAVEN/SEP has different • Moving to 3.3V digital for most parts- Some parts (MUX) require Voltage (3.3V to 5.0 V) converters (UT54ACTS244). • THEMIS Spin pulse features disabled (S/C not spinning) • Comparator is different (faster). (all other parts are identical) • Add new Burst feature to FPGA (no change to hardware)

31. Electronics Block Diagram Signal chain: 1 of 6 channels shown 5 Different Digital to Analog interfaces: 3 quad DACs 7 ADCs 1 MUX Bias oscillator Test pulser Bias Voltage Test Pulser DAC DAC Gain + shaping Thresh FPGA Coincidence Logic & Accumulators PD A250F Preamp Shaper ADC Memory BLR DFE Board DAP Board

32. Controller Schematic SEP will follow MAVEN design rules for these

33. FPGA Schematic All pinouts subject to change

34. Analog Housekeeping ADC

35. Test Pulse and Bias Control

37. Peak Digitizer

38. Bias Supply

39. FPGA Requirements • FPGA Requirements • FPGA Controls 6 ADC channels • FPGA receives input (asynchronously) from the VALID Signal and PEAK detect comparators. • FPGA wakes up ADC when VALID is received (400 ns max) • FPGA controls CONVERT and READ signals based on PEAK • FPGA monitors and resets BASELINE restore • FPGA Controls analog house keeping ADC and associated MUX • FPGA Receives CDI commands • FPGA Loads Lookup Tables • FPGA determines coincidence pattern (FTO) for each Telescope (TID) • FPGA sums ADC energy value of all coincidence channels • Energy value (12bits) (*), FTO pattern (3bits) and TID (1 bit) used to lookup Histogram bin (1 Byte) • FPGA increments histogram bin by 1 (2 byte accumulator). • FPGA periodically samples each channel in absence of pulse to determine noise level. Noise histograms stored separately • FPGA runs background checksum of Tables • FPGA stores raw events in extra memory to detect burst events (NEW) (64 kbytes are free) • FPGA sends messages to PFDPU • Data accumulations 1 per second • Analog Housekeeping values/ Digital Monitors • Noise histograms • Burst messages • Update rate of DACs is TBR (probably software controlled) New requirements shown in red See MAVEN_SEP_FPGA_?.doc for details

40. Inputs signals (and some output signals) are asynchronous and require conditioning in the FPGA

41. Coincidence determined in same manner as on THEMIS: • FTO pattern latched on (falling) edge of PEAK (when LLD is high) for each channel of triplet stack. FTO pattern of all channels must match to be valid.

42. New Burst Feature • This mode will only be added if sufficient ACTEL gates and resources (time) are available in the FPGA. The purpose is to look for rapid (non Poisson) bursts of counts that one might expect from bursts of particles or x-rays (for example from a lightning burst). Since a one second accumulation of data is insufficient to resolve phenomena that occur on the 1 ms time scale, we propose a burst mode that saves events in a circular buffer, with a triggered readout. Mode can be disabled if needed.

43. For each event record the following 3 bytes (TBR) of info: • 1 bit TID • 3 bit FTO • 12 bit Energy • 8 bit Delta Time (DT) (resolution of ~100 usec) • Also accumulate a delta time histogram of events cleared every 1sec (TBR). • The triggering mechanism will be based on total number of number of events less than DT threshold exceeding limit (programmable) l • Further details need to be resolved with FPGA programmer.