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Inst Mem. IAD. Control. Addr. Addr. WAD. RA1. RA2. Input. Output. M- Reg. LDM. WOUT. OpCode. Reg File. EMR. EALU. EI. A L U. S H I F T. WM. Mem Unit. RM. WR. SC. WA. Addr. EM. WAD. Storing Control. We need a memory to store control
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Inst Mem IAD Control Addr Addr WAD RA1 RA2 Input Output M- Reg LDM WOUT OpCode Reg File EMR EALU EI A L U S H I F T WM Mem Unit RM WR SC WA Addr EM WAD Storing Control • We need a memory to store control • This memory has its own address • Inst memory address can be loaded • Inst memory address can be incremented
Inst Mem IAD Control Addr Addr WAD RA1 RA2 Input Output M- Reg LDM WOUT OpCode Reg File EMR EALU EI A L U S H I F T WM Mem Unit RM WR SC WA Addr EM WAD Exercising Control • Control sequences are stored in mmeory • In each clock cycle, one step is executed • Sometime the address needs to be modified • It uses state of the program
Inst Mem IAD Control Addr Addr WAD RA1 RA2 Input Output M- Reg LDM WOUT OpCode Reg File EMR EALU EI A L U S H I F T WM Mem Unit Cond Code RM WR SC WA Addr EM WAD Condition Code • ALU generate status bits like • carry, overflow, sign, and zero • zero=1 means result from ALU is zero • These bits can be used to change flow of program • A new address is generated using CCs