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ECE 551 - FPGA Design: Breakout

ECE 551 - FPGA Design: Breakout. Semester Project Final Presentation Derek Rose Richard Wunderlich. Game Description. Classic Breakout game Pong-like arcade game from the late ‘70s Use the paddle to bounce the ball Hit the bricks with the ball to break through all of the rows.

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ECE 551 - FPGA Design: Breakout

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  1. ECE 551 - FPGA Design:Breakout Semester Project Final Presentation Derek Rose Richard Wunderlich

  2. Game Description • Classic Breakout game • Pong-like arcade game from the late ‘70s • Use the paddle to bounce the ball • Hit the bricks with the ball to break through all of the rows November 29, 2007

  3. Hardware Setup • Spartan-3 Startup Kit Demo Board • Xilinx Spartan-3 FPGA • Serial, VGA, PS/2, Expansion ports • 2Mbit Flash • 1Mbit SRAM • Monitor • Keyboard November 29, 2007

  4. Component Requirements • VGA interface • Output playing field, score, lives, etc. • PS/2 interface • Control paddle with a mouse or a keyboard • Switches and buttons • Game settings • Paddle control • Reset game • LEDs • Debug information (button status) • 7-Segment LED display • Debug information (ball location) November 29, 2007

  5. System Overview • BIST • Video test • LED output of pushbutton status • Breakout Logic • Control game • External hardware • Monitor • Keyboard Keyboard November 29, 2007

  6. Project Schematic November 29, 2007

  7. Problems Encountered • VGA display driver • Display signal timing (color fading) • Signal pipelining, synchronization • Mouse driver • Two-way PS/2 communication • Data pre processing • Game logic • Ball reflections off of the bricks proved to be very difficult to handle correctly November 29, 2007

  8. Project Statistics (Xilinx) Number of Slices: 1329 out of 1920 69% Number of Slice Flip Flops: 768 out of 3840 20% Number of 4 input LUTs: 2365 out of 3840 61% Number used as logic: 1979 Number used as a route-thru: 380 Number used as Shift registers: 6 Number of bonded IOBs: 40 out of 173 23% IOB Flip Flops: 18 Number of GCLKs: 6 out of 8 75% Total equivalent gate count for design: 25,566 out of 200,000 13% November 29, 2007

  9. Project Statistics (Altera) Total logic cells (LC): 2599 out of 3744 69% Number of LUT-only LC’s: 1936 Number of Register-only LC’s: 317 Number of LUT/Register LC’s: 346 Total pins: 35 out of 189 18% Total memory bits: 0 out of 18,432 0% November 29, 2007

  10. Results / Lessons Learned • Game implemented and playable • Many VHDL tips and tricks learned • Timing and synchronicity are difficult issues to understand and debug • Device drivers must be perfected before incorporation into your design • Make your code easy to reuse! • …so that I can use it to do a project later November 29, 2007

  11. Live Demo November 29, 2007

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