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Vishwani D. Agrawal James J. Danaher Professor Dept. of Electrical and Computer Engineering

ELEC 5270/6270 Spring 2013 Low-Power Design of Electronic Circuits Pass Transistor Logic: A Low Power Logic Family. Vishwani D. Agrawal James J. Danaher Professor Dept. of Electrical and Computer Engineering Auburn University, Auburn, AL 36849 vagrawal@eng.auburn.edu

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Vishwani D. Agrawal James J. Danaher Professor Dept. of Electrical and Computer Engineering

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  1. ELEC 5270/6270 Spring 2013Low-Power Design of Electronic CircuitsPass Transistor Logic: A Low Power Logic Family Vishwani D. Agrawal James J. Danaher Professor Dept. of Electrical and Computer Engineering Auburn University, Auburn, AL 36849 vagrawal@eng.auburn.edu http://www.eng.auburn.edu/~vagrawal/COURSE/E6270_Spr13/course.html ELEC6270 Spring 13, Lecture 12

  2. Low-Power Logic Styles • Pass transistor logic • Dynamic logic • Domino logic • Adiabatic and charge recovery logic • Asynchronous logic • Logic restructuring ELEC6270 Spring 13, Lecture 12

  3. Pass Transistor Logic (PTL) • Requires fewer transistors • Smaller area • Reduced capacitance • Reduced energy and power ELEC6270 Spring 13, Lecture 12

  4. CMOS AND Gate A F = AB B A F = AB B ELEC6270 Spring 13, Lecture 12

  5. Pass Transistor AND Gate B A F = AB 0 Need 4 transistors instead of 6 for CMOS AND gate. ELEC6270 Spring 13, Lecture 12

  6. CMOS OR Gate A B F = A + B A F = A + B B ELEC6270 Spring 13, Lecture 12

  7. Pass Transistor OR Gate B 1 F = A + B A Need 4 transistors instead of 6 for CMOS OR gate. ELEC6270 Spring 13, Lecture 12

  8. Reduced Voltage Swing IN Vx = VDD – Vtn OUT VDD = 2.5V n transistors, W/L = 0.5μ/0.25μ p transistors, W/L = 1.5μ/0.25μ ELEC6270 Spring 13, Lecture 12

  9. Spice Simulation 3.0 2.0 1.0 0.0 IN Vx Voltage, V OUT 0 0.5 1.0 1.5 2.0 Time, ns J. M. Rabaey, A. Chandrakasan and B. Nokolić, Digital Integrated Circuits, Upper Saddle River, New Jersey: Pearson Education, 2003. ELEC6270 Spring 13, Lecture 12

  10. Voltage Transfer Characteristic (VTC) of AND Gate B A F = AB 0 n transistors, W/L = 0.5μ/0.25μ p transistors, W/L = 1.5μ/0.25μ ELEC6270 Spring 13, Lecture 12

  11. VTC: Spice Simulation 3.0 2.0 1.0 0.0 VDD – Vtn B = VDD A = 0 → VDD F, V A = VDD, B = 0 → VDD A = B = 0 → VDD 0 0.5 1.0 1.5 2.0 2.5 Vin, V ELEC6270 Spring 13, Lecture 12

  12. Energy If this voltage is insufficient for turning the pMOS Transistor in inverter off, leakage power will be consumed. 0 → VDD Vout VDD = 2.5V i(t) CL T T E0→1 = ∫ P(t) dt = VDD ∫ i(t) dt 0 0 VDD-Vtn = VDD ∫ CL dVout = CL VDD (VDD – Vtn) < CL VDD2 0 ELEC6270 Spring 13, Lecture 12

  13. Energy: PTL vs. CMOS • PTL consumes less dynamic power than static CMOS Logic. • PTL leakage may be higher when inverter output is low, because the reduced voltage level may be insufficient to turn the PMOS transistor in the inverter off. ELEC6270 Spring 13, Lecture 12

  14. Ways to Reduce Leakage • Level restoration • Multiple-threshold transistors • Transmission-gate logic ELEC6270 Spring 13, Lecture 12

  15. Level Restoration VDD Level restorer B=1 Vout A=1 0 CL Level restorer device should be weaker than the nMOS pass transistor. Otherwise, VDD → 0 transition at Vout will be impossible. ELEC6270 Spring 13, Lecture 12

  16. Multiple-Threshold Transistors • Use zero-threshold pass-transistors. • Use high-threshold transistors in all other gates. • This can cause leakage through multiple gates. ELEC6270 Spring 13, Lecture 12

  17. Leakage Through Zero-Threshold Transistors Zero or low-threshold transistors 1 0 Leakage current path 0 1 ELEC6270 Spring 13, Lecture 12

  18. Transmission-Gate Logic • Provides both power and ground levels. • Good design, except needs more transistors. Inverting multiplexer A S B F F’ = S’A’ + SB’ ELEC6270 Spring 13, Lecture 12

  19. Transmission-Gate XOR B AB’+A’B A ELEC6270 Spring 13, Lecture 12

  20. A Logic Library ELEC6270 Spring 13, Lecture 12

  21. CMOS Multiplexer A S B INV02 MULTIPLEXER AND-OR-INVERT (AOI22) ELEC6270 Spring 13, Lecture 12

  22. CMOS Multiplexer Cell S S B S A B A S S S F ELEC6270 Spring 13, Lecture 12

  23. Synthesis of PTL Shannon’s expansion: Z = AB + BC + AC = A(B+BC+C) + A’(BC) = A(B+C) + A’BC = A[B+B’C] + A’[BC+B’0] 1 C C 0 1 0 1 0 B 1 0 A Z ELEC6270 Spring 13, Lecture 12

  24. Synthesis of Z = AB + BC + AC 0 1 C B A A = 1, Z = B + B’C B = 1, Z = 1 B = 0, Z = C A = 0, Z = BC B = 1, Z = C B = 0, Z = 0 Z ELEC6270 Spring 13, Lecture 12

  25. Pass-Transistor Cell ELEC6270 Spring 13, Lecture 12

  26. Synthesis of Z = A’B + B’C + A’C’ A 0 B C = 1, Z = A’B + B’ B = 1, Z = A’ B = 0, Z = 1 C = 0, Z = A’ C Z ELEC6270 Spring 13, Lecture 12

  27. Synthesis of Z = A’ + BC’ + B’C C C’ 0 B B’ A A’ A = 1, Z = BC’ + B’C B = 1, Z = C’ B = 0, Z = C A = 0, Z = 1 Z ELEC6270 Spring 13, Lecture 12

  28. Synthesis of Z = AB’C’ + A’B’C C’ C 1 A = 1, Z = B’C’ B = 1, Z = 0 B = 0, Z = C’ A = 0, Z = B’C B = 1, Z = 0 B = 0, Z = C A’ A B’ B Z ELEC6270 Spring 13, Lecture 12

  29. CPL: Complementary Pass-Transistor Logic • Every signal and its complement is generated. • Gates are static, because the output is connected to either VDD or GND. • Design is modular; same cell can produce various gates by simply permuting the input signals. • Also called differential pass-transistor logic (DPL) ELEC6270 Spring 13, Lecture 12

  30. A CPL Cell ELEC6270 Spring 13, Lecture 12

  31. CPL Cell Used As AND/NAND B B’ ABA’ B’ Z = AB Z’ = (AB)’ ELEC6270 Spring 13, Lecture 12

  32. CPL Cell Used As OR/NOR B’ B ABA’ B’ Z = A + B Z’ = (A + B)’ ELEC6270 Spring 13, Lecture 12

  33. CPL Cell Used As XOR/XNOR B’ B AA’A’ A Z = AB’ + A’B Z’ = AB + A’B’ ELEC6270 Spring 13, Lecture 12

  34. CPL vs. CMOS • CPL requires fewer transistors. • Useful for modular (array) circuits like adders, multipliers, barrel shifter, etc. • CPL operation can be faster and energy efficient. • Following example is taken from: • M. E. Elrabaa, I. S. Abu-Khater, and M. I. Elmasry, Advanced Low-Power Digital Circuit Techniques, Springer, 1997, Chapter 2. ELEC6270 Spring 13, Lecture 12

  35. Example: 4-Bit Carry Select Adder A_1 B_1 Adder cell S1’ S0’ C0’ C0 C1’ C1 A_3 B_3 Adder cell S1’ S0’ C0’ C0 C1’ C1 A_2 B_2 Adder cell S1’ S0’ C0’ C0 C1’ C1 A_4 B_4 Adder cell S1’ S0’ C0’ C0 C1’ C1 M M M M M M M M M M M M M M M M M M M M C’_2 C’_4 C_4 C’_0 C_0 S_2 S_1 S_3 S_4 ELEC6270 Spring 13, Lecture 12

  36. CMOS Carry-Select Adder Cell Ai Bi S1’ S0’ C0’ C0 C1’ C1 ELEC6270 Spring 13, Lecture 12

  37. CPL Adder Cell Ai Bi S1’ S0’ C0’ C0 C1’ C1 ELEC6270 Spring 13, Lecture 12

  38. CPL Multiplexer Cell in2 in1 M Ci Ci out Ci’ Ci’ in2 in1 ELEC6270 Spring 13, Lecture 12

  39. 32-Bit Adders in 0.8μ, 3.3V ELEC6270 Spring 13, Lecture 12

  40. References • G. R. Cho and T. Chen, “On the Impact of Technology Scaling on Mixed PTL/Static Logic,” Proc. IEEE Int. Conf. Computer Design, 2002. • R. Zimmermann and W. Fichtner, “Low-Power Logic Styles: CMOS Versus Pass-Transistor Logic,” IEEE J. Solid State Circuits, vol. 32, no. 7, pp. 1079-1090, July 1997. ELEC6270 Spring 13, Lecture 12

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