Towards Minimal Explanations of Unsynthesizability for High-Level Robot Behaviors

1. Towards Minimal Explanations of Unsynthesizability for High-Level Robot Behaviors Hadas Kress-Gazit Sibley School of Mechanical and Aerospace Engineering Cornell University Vasu Raman Department of Computing and Mathematical Sciences California Institute of Technology

2. High-Level Tasks: Carrying meals to patients Delivering medical records Patrolling patient rooms . . . http://newsroom.ucla.edu/portal/ucla/artwork/4/5/7/9/4/245794/EVA_Robot_3-c.jpg

3. High-Level Tasks: Carrying meals to patients Delivering medical records Patrolling patient rooms Challenges: Easy to instruct Does as it is told* http://newsroom.ucla.edu/portal/ucla/artwork/4/5/7/9/4/245794/EVA_Robot_3-c.jpg

4. Example public rooms patient rooms Carry meals from the kitchen to all patient rooms.

5. Example public rooms patient rooms Start in the closet. Carry meals from the kitchen to all patient rooms. Don’t go into any public rooms.

6. Continuously implement discrete solution Synthesize correct discrete solution Create abstraction ofproblem User-defined specification Formal Methods for High-Level Control Natural language Template-based grammar Temporal logic Transition systems …

7. Continuously implement discrete solution Synthesize correct discrete solution Create abstraction ofproblem User-defined specification Formal Methods for High-Level Control Natural language Template-based grammar Temporal logic Transition systems … • Fainekos, Kress-Gazit and Pappas, ICRA 2005 • Kress-Gazit, Fainekos and Pappas, ICRA 2007 • Kloetzer and Belta, TAC 2008 • Karaman and Frazzoli, CDC 2009 • Bhatia, Kavraki and Vardi, ICRA 2010 • Wongpiromsarn, Topcu and Murray, HSCC 2010

8. Controller Synthesis Overview (LTLMoP* Toolkit) (FSM) Specification Synthesizable Synthesis Unsynthesizable ? Hybrid Controller Simulation Physical Robot *http://ltlmop.github.io/

9. Controller Synthesis Overview (LTLMoP* Toolkit) (FSM) Specification Synthesizable Synthesis Unsynthesizable Specification Analysis + Feedback to the User Hybrid Controller Simulation Physical Robot *http://ltlmop.github.io/

10. Controller Synthesis Overview (LTLMoP* Toolkit) (FSM) Specification Synthesizable Synthesis Unsynthesizable Specification Analysis + Feedback to the User Hybrid Controller Change the Specification Simulation Physical Robot *http://ltlmop.github.io/

11. Controller Synthesis Overview (LTLMoP* Toolkit) (FSM) Specification Synthesizable Synthesis Unsynthesizable Specification Analysis + Feedback to the User Hybrid Controller This talk Change the Specification Simulation Physical Robot *http://ltlmop.github.io/

12. Form of Specification Environment assumptions Desired guarantees UNSYNTHESIZABLE Unsatisfiable Unrealizable Two levels of analysis: - identify subformulas that contribute - compute minimal subformula causing failure

13. Form of Specification Environment assumptions Desired guarantees UNSYNTHESIZABLE Unsatisfiable Unrealizable Two levels of analysis: - identify subformulas that contribute - compute minimal subformula causing failure

14. Problem Statement • Highlight a MINIMAL cause of unsynthesizability • Find a small subformula ’ of such that: • ’ is by itself unsynthesizable • (an unsynthesizable “core”) •  every proper subformula of ’ is synthesizable

15. Linear Temporal Logic (LTL) Syntax is a set of atomic propositions, Semantics : infinite sequence of truth assignments satisfies next always eventually Time

16. Unsatisfiable Cores via propositional satisfiability (SAT) • General Idea: • “Unroll” LTL specification to some depth • (encode as a propositional SAT problem) • Use off-the-shelf SAT solver to find MUS • Given a MUS, map it back to the LTL

17. Unsatisfiable Cores via propositional satisfiability (SAT) • Unrolling the LTL specification: • Fix unroll depth d • Construct SAT instance •  /\ /\ /\ /\ … /\ • e.g. always wave  wave1 /\ wave2 /\ … /\ waved 1 2 3 0 d

18. Unsatisfiable Cores via propositional satisfiability (SAT) • Use off-the-shelf SAT solver to find MUS: • Input – unrolled specification in CNF form • Output – Subset of CNF clauses • e.g. PicoSAT* *http://fmv.jku.at/picosat/

19. Unsatisfiable Cores via propositional satisfiability (SAT) • Given an MUS, map it back to the LTL: • Track origin of each CNF clause • Depth of unrolling determines “core” found

20. Unrealizable “Cores” Unsatisfiable variables Unrealizable X UY environment-controlled robot-controlled Unsatisfiability: no assignment to X UY satisfies Unrealizability: exists assignment to X such that no assignment toYsatisfies

21. Unrealizable “Cores” Unsatisfiable variables Unrealizable X UY environment-controlled robot-controlled • Can we still use SAT-based techniques? • Yes, but we need to restrict the environment variables X in the “right” way

22. Unrealizable “Cores” Unsatisfiable variables Unrealizable X UY environment-controlled robot-controlled Counterstrategy + SAT-based techniques: • Unroll the specification as before • Restrict inputs according to environment counterstrategy • Compute MUS of resulting SAT formula

23. Unrealizable “Cores”

24. Unrealizable “Cores”

25. Start in the closet. Carry meals from the kitchen to all patient rooms. Don’t go into any public rooms.

26. Towards Minimal Explanations of Unsynthesizability for High-Level Robot Behaviors Vasu RamanHadas Kress-Gazit vasu@caltech.eduhadaskg@cornell.edu