Computer Architecture & Operations I

1. Instructor: Yaohang Li Computer Architecture & Operations I

2. Review • Last Class • Basic of Logic Design • This Class • Assignment 2 • Integrated Circuits • Decoder • Multiplexor • PLA • ROM • Don’t Care • Bus • Next Class • Design of ALU

3. Integrated Circuit • Integrated Circuit (IC) • A small electronic device made out of a semiconductor material • Classifications • SSI (small-scale integration) • up to 100 electronic components per chip • MSI (medium-scale integration) • 100~3,000 electronic components per chip • LSI (large-scale integration) • 3,000~100,000 electronic components per chip • VLSI (very large-scale integration) • 100,0000 to 1,000,0000 electronic components per chip • ULSI (ultra large-scale integration) • More than 1 million electronic components per chip

4. Decoder • Decoder • A logic block that has n-bit input and 2n outputs, where only one output is asserted for each input combination • If the input is i (in binary), • then output i is 1 • others are 0

5. Decoder Example • 3-8 Decoder

6. Multiplexor • Multiplexor • A selector • The output is selected by an input control

7. Implementation of a Multiplexor

8. n-input Multiplexor • A Multiplexor can have n-inputs • Require selective inputs • Implementation of an n-input Multiplexor

9. Two-level Logic • Try to Remember: Any Boolean Logic function can be implemented with only NOT, AND, OR functions • We can also find that all logic functions can be written in a canonical form • Sum of Product • Logical Sum (OR) of terms joined by Product (AND) • Product of Sum • Logical Product (AND) of terms joined by Sum (OR)

10. Example • Consider a logic function • Equivalent to sum of products • Equivalent to product of sums

11. In Class Exercise • Considering the following truth table for D, write the function of D using sum of products

12. Answer • Combinations that D is 1 • Answer

13. Programmable Logic Array • Programmable Logic Array (PLA) • Two stages of logic • An array of AND gates (product terms) • An array of OR gates

14. PLA Example • Considering the following table, implement the PLA for D, E, F

16. Another PLA Representation • Dot in the AND plane • Input, or its inverse, occurs in the product term • Dot in the OR plane • Corresponding product term appears in the corresponding output

17. Read Only Memory • Read Only Memory (ROM) • Has a set of locations that can be read • Contents of these locations are fixed • Programmable ROM (PROM) • Can be burnt using a device called a “ROM programmer” • Erasable Programmable Read Only Memory (EPROM) • Data in the ROM can be deleted under ultra-violet rays • EEPROM (Electrically Erasable Read Only Memory) • Data in the ROM can be erased by a simple electric current

18. ROM • Height • m inputs • 2m addressable entries (input lines) • Width • n outputs (functions) • 2n output bits • mxn is the shape of the ROM

19. ROMs and PLAs • PLA is partially decoded • ROM is fully decoded • Contains a full output word for every possible input combination • Always contain more entries than PLA ROM (8 entries – 1 unused) PLA (7 entries)

20. Don’t Care • Don’t Care • We don’t care about the actual values • Output Don’t Care • We don’t care about the value of an output for some input combination • Input Don’t Care • An output only depends on some of the inputs • Advantages of Don’t Care • Easier to optimize the implementation of a logic function

21. Example of Don’t Cares • Original Truth Table

22. Example of Don’t Cares • Output Don’t Cares • Input Don’t Cares

23. Array of Logic Elements • Bus • In logic design, a collection of data lines that is treated together as a single logical signal • Shared collection of lines with multiple sources 32-bit wide 2-to-1 multiplexor

24. Summary • Integrated Circuits • Decoder • Multiplexor • PLA • ROM • Don’t Care • Bus

25. What I want you to do • Review Chapter 1