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The Process flow for fabrication the resister IC

1. The Process flow for fabrication the resister IC. Step I: The Beginning-Choosing a substrate Before actual wafer fabrication, we must choose the starting wafers. The major choices are the type (N or P), resistivity, and orientation.

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The Process flow for fabrication the resister IC

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  1. 1 The Process flow for fabrication the resister IC Step I: The Beginning-Choosing a substrate Before actual wafer fabrication, we must choose the starting wafers. The major choices are the type (N or P), resistivity, and orientation. In most IC circuits, the substrate has a resistivity in the range of 25- 50cm, which corresponds to a doping level on the order of 1015cm-3. The other major parameter we need to specify in the starting substrate is the crystal orientation. Virtually all modern silicon integrated circuits are manufactured today from wafer with a (100) surface orientation. The principal reason for this is that the properties of Si/Sio2 interface are significantly better when a (100) crystal is used. Lecture # 2

  2. CMOS Process Flow

  3. Cross section of the final CMOS integrated circuit.

  4. 3SiH4+4NH3Si3N4+12H2 Silicon nitride form a barrier against the impurities moving toward the Si surface.

  5. 4 Photolithography • In order to transfer resister information from the design to the wafer, a process known as photolithography is used. • For this process a material known as photoresist is first spread on the wafer. It is usually baked at about 100oC in order to drive off • solvants from the layer (photolithographic process will be covered in chapter 5 through. Lecture # 2

  6. Open windows for thick oxidation

  7. Bird’s beak

  8. P Well Formation 1016 -1017 cm-3

  9. N Well Formation

  10. High temperature Drive-In 2-3 micron

  11. NMOS gate formation and adjusting VTH The single most important parameter in the both NMOS and PMOS devices is the threshold voltage To adjust VTH , two terms that are important are the doping concentration and the oxide capacitance.

  12. PMOS Gate Formation

  13. Regrown of gate oxide Why oxide layer is stripped and then regrown?

  14. Deposition of polysilicon layer SiH4 Si+2H2 Low ploy sheet resistivity and low gate resistance is required.

  15. Selective Etching: to locate MOS gates Selectivity and anisotropy are big deal hare

  16. Tip or extension (LDD) formation

  17. Tip or extension (LDD) formation

  18. Sidewall Spacer fabrication

  19. Aniostropic Etching

  20. Formation of NMOS source and Drain region

  21. Formation of PMOS source and Drain region

  22. High temperature Drive-In TED is a big issue hare!

  23. Contact and local Interconnect formation

  24. TiSi2

  25. Multilevel metal formation

  26. 8 Basic NMOS process flowchart. Lecture # 2

  27. 9 Basic bipolar process flowchart. Lecture # 2

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