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2011 VLSI Test Symposium

An Efficient Test Data Reduction Technique Through Dynamic Pattern Mixing Across Multiple Fault Models. S. Alampally 1 , R. T. Venkatesh 2 , P. Shanmugasundaram 2 R. A. Parekhji 1 and V. D. Agrawal 2 1 Texas Instruments, Bangalore (India) 2 Auburn University, Alabama (USA).

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2011 VLSI Test Symposium

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  1. An Efficient Test Data Reduction Technique Through Dynamic Pattern Mixing Across Multiple Fault Models S. Alampally1, R. T. Venkatesh2, P. Shanmugasundaram2 R. A. Parekhji1 and V. D. Agrawal2 1Texas Instruments, Bangalore (India) 2Auburn University, Alabama (USA) 2011 VLSI Test Symposium

  2. Outline • Pattern optimization across fault models • Concurrent ATPG flow • Results • Observations • Conclusion VLSI Test Symposium 2011

  3. Limited number of tester channels and channel bandwidth Testing costs overview Tester memory constraints Cost of adding testability hardware on chip Reference: N. A. Touba, “Survey of Test Vector Compression Techniques,” IEEE Design & Test of Computers, Vol. 23, pp. 294-303, Apr. 2006. VLSI Test Symposium 2011

  4. Pattern optimization across fault models Path Delay Transition Bridging Stuck-At Methodology Optimized Pattern Set VLSI Test Symposium 2011

  5. Prior work on pattern reuse [1] N. Yogi and V. D. Agrawal, “N-Model Tests for VLSI Circuits,” Proc. 40th IEEE Southeastern Symposium on System Theory, pp. 242-246, March 2008. [2] S. Goel and R. A. Parekhji, “Choosing the Right Mix of At-Speed Structural Test Patterns: Comparisons in Pattern Volume Reduction and Fault Detection Efficiency,” Proc. 14th IEEE Asian Test Symposium, pp. 330-336, Dec. 2005. • N. Yogi and V. Agrawal [1] explored the use of hybrid LP-ILP for static pattern optimization. - Experiments were carried out on ISCAS89 benchmarks. - Stuck-at, transition and IDDQ combinations were considered. - More than 50% reduction in pattern count was achieved. • S. Goel and R. Parekhji [2] described a technique for pattern optimization for delay faults. - Path delay, transition fault and stuck-at models were considered. - Benefit of (ΔA + ΔB + C) versus (A + B + C). - Pattern count reductions of up to 37% were observed. - Employed by several teams in TI. • We will later compare the advantage of the current work against [2]. VLSI Test Symposium 2011

  6. Concurrent ATPG flow with example Pattern interval 1 Pattern interval 2 Pattern interval 3 VLSI Test Symposium 2011

  7. Saved patterns metric • Pattern set that is chosen and saved in an interval is decided based on an effectiveness criteria. • SPS (Saved Patterns) is defined as the number of patterns saved if pattern set PS is chosen over the other set PT. • This effectiveness criteria is computed as, SPS = IFSC(PS,FT) * PT/IFCT and SPT = IFSC(PT,FS) * PS/IFCS. • The pattern set that gives the ‘highest’ savings in an interval is chosen and saved based on this metric. VLSI Test Symposium 2011

  8. Designs used for evaluating the concurrent ATPG flow Concurrent ATPG runs were conducted using different fault model combinations and the results were analyzed. VLSI Test Symposium 2011

  9. Results in non-compression mode VLSI Test Symposium 2011

  10. Results with test compression VLSI Test Symposium 2011

  11. Observations Bridging fault coverage when run along with transition and path delay fault models. Transition fault coverage when run along with dynamic bridging and path delay fault models. When compared against just summing up patterns across fault models and also the technique of [2], concurrent ATPG provides good benefit for designs irrespective of the use of test compression . Percentage reduction in pattern count was lesser with designs using test compression when compared to the same designs without enabling compression. VLSI Test Symposium 2011

  12. Observations Path delay fault coverage when run along with transition and bridging fault models. When path delay model is used with two other models with the concurrent ATPG, it gets sidelined due to the domination by the other two. Run times can be large compared to the existing optimization technique because of the ATPG and fault-simulation runs at each interval. VLSI Test Symposium 2011

  13. Conclusion Test data volume and test time are critical components of test cost because of tester memory constraints. In this work an ATPG technique is proposed where all fault models are concurrently targeted in a single ATPG run and pattern count reduction is achieved. Reductions ranging from 21% to 68% were seen compared to the approach of just adding patterns across models (unoptimized). 3% to 36% improvements were seen over the existing optimization technique. VLSI Test Symposium 2011

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