Statistical Timing in a Practical 65 nm Robust Design Flow

1. Statistical Timing in a Practical65 nm Robust Design Flow Chandu Visweswariah

2. The power of statistical formulas Statistical Timing in a Practical 65 nm Robust Design Flow

3. Acknowledgements • The extended statistical timing, statistical optimization, timing support and timing methodology teams at IBM Yorktown, Fishkill, Burlington, Poughkeepsie, Rochester and Waltham Caveat • This presentation is mostly ASIC-focused, although microprocessor design issues will be mentioned(time permitting) Statistical Timing in a Practical 65 nm Robust Design Flow

4. Outline • Yield loss mechanisms and the tradeoffs involved • What is robust design? • A timing closure methodology based on statistical timing • Myths about statistical timing • Interesting challenges • early/late splits and CPPR • at-speed test • metrics for optimization • delay modeling for 45 nm • hierarchical statistical timing Statistical Timing in a Practical 65 nm Robust Design Flow

5. 100% 80% Defect Based Lithography Based 60% Yield Parametric (design-based) 40% 20% Source: NEC 0% 350nm 250nm 180nm 130nm 90nm Catastrophic vs. parametric yield loss Dummy fill Dummy fill Statistical Timing in a Practical 65 nm Robust Design Flow

6. Increasing and inevitable parametric variability Litho-induced variability Oxide thickness Random dopant effects* Interconnect CMP and RIE effects *D. J. Frank et al, Symp. VLSI Tech., 1999 Statistical Timing in a Practical 65 nm Robust Design Flow

7. We would like toretain these wafers Normalized metal resistance data over 3 months 3.0 • Wafer means change over time • Values are “out-of-spec,” need to yield within WAC limit 2.5 2.0 1.5 1.0 Statistical Timing in a Practical 65 nm Robust Design Flow

8. Lower spec. limit Upper spec. limit Nominal spec. Manufacturing for predictable performance • Cp and Cpk (Process Capability Indices) measure manufacturing predictability • Manufacturing typically (but not always) outperforms spec. limits Statistical Timing in a Practical 65 nm Robust Design Flow

9. Normalized cumulative statistics 1.0 1.5 2.0 2.5 • Distributions are not Gaussian (but usually close) Statistical Timing in a Practical 65 nm Robust Design Flow

10. Ring oscillator performance distribution Slower spec Percentage of chips • Color coding is by wafer • Hardware is faster/tighter than predictions Statistical Timing in a Practical 65 nm Robust Design Flow

11. Normalized metal resistance across manufacturing lines 0.368 0.448 0.528 0.608 0.688 0.768 0.848 0.928 0.44 0.52 0.60 0.68 0.76 0.84 0.92 1.0 • Designs must yield at multiple fabs. Statistical Timing in a Practical 65 nm Robust Design Flow

12. 250 200 150 100 50 0 1.0 More 1.053 1.105 1.158 1.211 1.265 1.318 1.371 1.423 1.476 1.529 1.582 1.635 1.688 Normalized single-level capacitance distribution • Variability is enormous! Statistical Timing in a Practical 65 nm Robust Design Flow

13. 90 nm 65 nm 45 nm Any performance left in worst-case design? Statistical Timing in a Practical 65 nm Robust Design Flow

14. What do we do with all this variability? As we know, There are known knowns. There are things we know we know.We also know There are known unknowns. That is to say We know there are some things We do not know.But there are also unknown unknowns, The ones we don't know We don't know. Donald H. Rumsfeld1 Knownknowns Knownunknowns Unknownunknowns Statisticaltiming andpower analysis 1Dept. of Defense news briefing, 2/12/02, linebreaks mine Statistical Timing in a Practical 65 nm Robust Design Flow

15. Robust circuit design • Its the sensitivities, stupid! First order model Statistical Timing in a Practical 65 nm Robust Design Flow

16. Can get across-parameter RSS relief Chip means Can get space-dependent relief SystematicACV Can get down-a-path RSS relief RandomACV Early Late Early Late Fast chip vs. slow chip Delay modeling Statistical Timing in a Practical 65 nm Robust Design Flow

17. Late RO delay Early Mean RO delay Fast chip Slow chip Model-to-hardware correlation Statistical Timing in a Practical 65 nm Robust Design Flow

18. Bounding distributions 1.0 1.5 2.0 2.5 • Bounding distributions provide protection from various sins! Statistical Timing in a Practical 65 nm Robust Design Flow

19. Statistical-timing-based flow • Conduct statistical timing with correlations • predict timing slacks in “canonical” form parameterized by the sources of variation • “Project” flop slacks to worst corner; if positive, we are safe • Get “debits” and “credits” • mixed-mode projection • spatial • coupling noise • independently random • Check sensitivities • alternative statement of Murphy’s law: “Variability exacerbates poor design!” • encourage “balanced” or “robust” design • Check single-corner timing with all bells and whistles • Optimization and fix-up • use incremental statistical timing • various diagnostics available Statistical Timing in a Practical 65 nm Robust Design Flow

20. Myths about statistical timing • “The main reason for statistical timing is within-die variations” … “Variability is dominated by within-die variations” … “The main frequency limiter is within-die variations” • Random dopants are the only truly statistical phenomena • “Statistical timing is a good idea so long as you don't assume that variations are statistical,” said TI's (Dennis) Buss. About the only thing that's truly statistical, he said, are random dopant fluctuations.” (From EE Times article 7/26/06 by Richard Goering) Statistical Timing in a Practical 65 nm Robust Design Flow

21. Courtesy Anne Gattiker, IBM Statistical Timing in a Practical 65 nm Robust Design Flow

22. Across-wafer variations Courtesy Anne Gattiker, IBM Statistical Timing in a Practical 65 nm Robust Design Flow

23. Undue pessimism Same buffer has different delays on early/late paths Interesting challenges: early/late splits and CPPR early clock LL3 LL1 LL2 CL late data Statistical Timing in a Practical 65 nm Robust Design Flow

24. Interesting challenges: at-speed testing Chip Under Test From tester: Clk Clock control Logic RefClk PLL StartTest Scan & Test Clocks Test Data PLL Output Clk Scan Clock Last Scan-Load Cycle At-Speed Test Scan Unload Cycles [Courtesy Gary Grise] Statistical Timing in a Practical 65 nm Robust Design Flow

25. Interesting challenges: at-speed testing • Each point in the process space can have a unique critical path • How to come up with a set of test vectors that testsfor parametric variations in all parts of the process space? • How to measure coverage thereof? • How to test against workload-related defects? • How to test against fatigue-related defects? Critical Critical Statistical Timing in a Practical 65 nm Robust Design Flow

26. Interesting challenges: metrics for optimization • Slack is lacking • different critical paths in different parts of the process space • slack is a distribution • slack does not give robustness information • relative ordering of paths • slack does not give correlation information Other open problems • Delay+power+noise variational modeling for 45 nm • Robust optimization, fix-up • Hierarchical robust design Statistical Timing in a Practical 65 nm Robust Design Flow

27. Conclusions • Must protect against parametric variability • high dimensionality, hence the need for statistical timing • hence the need for robust design • hence the need to check sensitivities • hence the need for statistical timing! • IBM has adopted a statistical-timing-based robust design flow for 65 nm ASICs • Many open and interesting challenges remain Statistical Timing in a Practical 65 nm Robust Design Flow