SET Fault Tolerant Combinational Circuits Based on Majority Logic

1. SET Fault Tolerant Combinational Circuits Based on Majority Logic M. Aykut YİĞİTEL CMPE 516 Department of Computer Engineering Bogazici University 17.05.2007

2. OUTLINE • Introduction • TMR, Analog Voter and Analog Inverter • AND and OR Gates Using Majority Logic • Fault Tolerant Implementation of an Adder • Comparison With the Traditional Technique • Conclusion • References

3. Introduction • The design of fault tolerant systems has been a concern since the inception of the computer industry. • As the technology, manufacturing process and test mechanisms evolved, the industry managed to produce components with ever increasing yield and reliability.

4. Introduction • More recently, systems designed for safety, critical missions, air and space applicaitons, among others, always deserved the development of specific desing techniques to make them tolerant to the so-called transient faults. • What is transient faults?

5. Transient Faults • Caused by radiation particles and other sources of interference (when ionizing energetic particles, such as protons or heavy ions). • Generates current pulses that affect, during a short period of time, the behaviour of digital circuits.

6. Transient Faults • Depending on the amplitude and duration of the transient pulse, as well as the exact moment and the part of the circuit in which it occurs, it may have different effects. • When the effect of the pulse is to change the value of the data of a flip-flop this is called a Single Event Upset (SEU). • When one pulse effects a single gate in a combinational circuit, this is called Single Event Transient (SET).

7. SEU Origin 10100001 00100001

8. Transient Faults • SET may lead to an erroneous value at the output of the gate or not, depending on the value of the inputs, the propagation delay, and of the logic function implemented by the gate. • For circuits with clock cycles much longer than the duration of SET pulses, the probability of the fault being latched is very low and usually neglected.

9. Transient Faults • For many years, fault tolerane community has been targeting mainly the problem of errors in storage devices, such as registers and memories, i.e. SEUs. • In combinational circuits, some tecniques, such as TMR and other using time or space redundancy, have also been developed for use in mission critical systems, always assuming that the probability of two or more simultaneous SETs occuring similtaneously is negligible.

10. Transient Faults • As technology continued to evolve, with ever decreasing device dimensions, lower operaing voltages and gate capacitances, and shorter cycle times, the concern with the influence of SETs in the behaviour of combinational circuits grew. • Traditional techniques (like TMR) can not cope with SET in combinational circuits, either because of their excessive cost, or because even TMR protected circuits can fail.

11. Why Beyond TMR? • TMR protects only against single faults in one of the modules

12. Why Beyond TMR? • When a single fault occurs in the voter circuit, the voter output may be wrong.

13. Analog Voter

14. Analog Voter

15. Analog Voter • The effect of a transient pulse on a transistor which is not transferring current, is to make it close, starting to transfer current and changing the value at the output. • However, when a transistor is already conducting a current, the additional current generated by the transient pulse does not change the output state and, therefore, does not harm the operation of the circuit.

16. Analog Voter

17. Analog Inverter • The same analog comparator used in previous slides as a voter can also be used as an analog inverter, which is also tolerant to SETs. Input Output Vref = Vdd/2

18. Using Majority Gates to Implement Combinational Functions • A 3 input majority gate implements the following logic function: • It is the same used to describe the behaviour of a TMR voter, which chooses among its three inputs the logic value which occurs 2 or 3 times. • Therefore, it’s possible to use the analog voter to replace a conventional majority gate. The resulting component is a SET tolerant majority gate.

19. Implementation of AND • When one of the 3 inputs is connected to ground, we have: • And the majority gate implements the AND operation.

20. Implementation of OR • Similarly, when connecting one of the inputs to Vdd we have: • And the majority gate implements the OR operation.

21. Using Majority Gates to Implement Combinational Functions • Connections to Vdd and to GND of the third input are done through pMOS or nMOS transistors. • Those transistors are always conducting current and, therefore, never fail when a transient pulse occurs. • Since the inputs fed into comparator must be inverted, the logic value of the third input of the AND circuit is 1 and the third input of the OR circuit is 0.

22. Analysis of a Fault Tolerant Implementation of an Adder • In order to confirm the fault tolerance characteristic of the components described before, this paper simulates the implementation of a full adder using majority logic(implemented with analog voters) and analog inverters(implemented with comparators), instead of conventional CMOS AND, OR and inverter gates.

23. Analysis of a Fault Tolerant Implementation of an Adder • This implementation has been compared with another one, using the conventional TMR technique, in which the adder is implemented using CMOS AND, OR and inverter gates and it is tripled, with the outputs(sum and carry) from three modules being voted also using a conventional digital voter(sum of products), implemented with CMOS gates.

24. Analysis of a Fault Tolerant Implementation of an Adder TMR Version Majority Gates Version

25. Analysis of a Fault Tolerant Implementation of an Adder • The area, propagation delay and power dissipation of the two alternative architectures have been estimated through simulation, using SMASH, a mixed-signal, multi-level SPICE simulator.

26. Analysis of a Fault Tolerant Implementation of an Adder • As we can see, the proposed solution brings a 36% reduction in the area required by the circuit, mainly due to the need to triplicate the functional part of the circuit in the TMR version.

27. Analysis of a Fault Tolerant Implementation of an Adder

28. Analysis of a Fault Tolerant Implementation of an Adder • When we look at power figures, they seem a drawback of the proposed architecture, as far as power consumption is concerned, since this is a major concern nowadays, mainly for circuits embedded in partable devices. • However, the 44% gain in performance gives us a good margin to trade performance for power consumption.

29. Analysis of a Fault Tolerant Implementation of an Adder • New simulations have been conducted in order to measure the power consumption if the same performance goal was maintained. • With this approach, the power consumption of the proposed solution fell to 200 µW, i.e., lower than that of the TMR approach for the same performances.

30. Analysis of a Fault Tolerant Implementation of an Adder • These results show that there is enough flexibility, in the proposed solution, to balance power consumption and performance according to the specific needs of the applicaiton, which allows faster circuits for non-portable devices and circuits with performance equivalent to that of TMR for portable systems. And, in both cases, with the same fault tolerance characteristics described previously.

31. Summary of the Analysis • The proposed technique has better area and speed than regular CMOS circuits. Although the proposed circuit dissipates more power than the equivalent CMOS, it must be noted that this power can be reduced by using the extra slack, for example, by using slower transistors, and working in the same speed regular CMOS would work, with less power dissipation, and still being SET tolerant.

32. Conclusion and Future Work • A new technique introduced, based on analog comparators, to implement combinational circuits that can withstand the effects of single event transients. • The basic concepts behind the use of analog comparators to implement voters for TMR systems and also majority gates have been explained.

33. Conclusion and Future Work • Simulations of the implementation of a full adder using the proposed technique and TMR have been compared, showing that the proposed solution is suitable for the purpose of protecting combinational circuits against single event transients with advantages in area occupation, when compared to the conventional TMR approach, and also allowing for adjustments between speed and power consumption, according to the target applicaiton of the circuit.

34. Conclusion and Future Work • Authors of the article intends to implement more complex circuits and submit those further experiments, aiming the applicaiton of the proposed solution in industrial desings. • Also, in order to face the growing probability of occurence of multiple similtaneous faults, one future work will be simulate the injection of double faults in circuits constructed using the approach proposed in this paper.

35. References • Michels, A., Petroli, L. Lisboa, C. A. L., KAstensmidt, F. And Carro, L. “SET Fault Tolerant Combinational Circuits Based on Majority Logic” Preceedings of the 21 st IEEE International Symposium on Detect and Fault-Tolerance in VLSI systems 2006. • E. Mikkola, B. Vermeire, H. J. Barnaby, H. G. Parks and K.Borhani, “SET Tolerant CMOS Comparator”, IEEE Transactions on Nuclear Science, December 2004. • Carlos A. L. Lisboa, Erik Schüler, Luigi Carro, “Going Beyond TMR for Protection against Multiple Faults”, in proceedings of the 18th Symposium on Integrated Circuits and System Desing – SBCCI 2005, Sociedade Brasileria de Computaçao, Florianopolis, September 4-7.

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