A CMOS low power, quad channel, 12 bit, 40Ms/s pipelined ADC for applications in particle physics calorimetry

1. A CMOS low power, quad channel, 12 bit, 40Ms/s pipelined ADC for applications in particle physics calorimetry Gonçalo Minderico minderic@chipidea.com 9th Workshop on Electronics for LHC Experiments

2. Outline • System Introduction • ADC Macro • Pipeline Architecture • Design Details • Experimental Results • Summary & Planning 9th Workshop on Electronics for LHC Experiments

3. System architecture System Introduction • Key factors • Low power consumption; high resolution; high speed • Input sampling rate 40Ms/s • Input signal bandwidth 5MHz • Channel selection • Radiation tolerant implementation Operating Modes 9th Workshop on Electronics for LHC Experiments

4. ADC Macro • Pipeline Architecture • Stage Resolution Tradeoff • > Nbit/stage • better static linearity • more complex blocks • Less modularity • < Nbit/stage • fastest time response • worst static linearity • simple to implement • FE 2b5 : area=0.38mm2; power=9.7mW • BE 1b5 : area=0.095mm2; power=1.9mW • Pipeline Architecture 9th Workshop on Electronics for LHC Experiments

5. Pipeline Architecture MDAC1b5 a) Gain=2 b) Flash output=2bit c) Flash SH not necessary 9th Workshop on Electronics for LHC Experiments

6. Design Details 2b5 MDAC opamp schematic 9th Workshop on Electronics for LHC Experiments

7. Design Details • Non-idealities • Comparator offset • MDAC gain error • Thermal noise Gain >4 Comp offset > Vref/8 Gain <4 9th Workshop on Electronics for LHC Experiments

8. Experimental Results • ADC Specs Definition 9th Workshop on Electronics for LHC Experiments

9. DNL/INL Results Fs=40Ms/s; Fin=2.5MHz • Internal references are disabled on following tests • VREF layout routing problem limits ADC performance • DNL < 0.7LSB • INL < 1.5LSB 9th Workshop on Electronics for LHC Experiments

10. SNR Results Supply 2.5V Fs=40Ms/s SNR [dB] vs Input signal freq [MHz] Fs=40Ms/s Fin=2.5MHz SNR=68dB SNDR=67dB ENOB=10.8bit SNR [dB] vs Input signal ampl [dBFS] 9th Workshop on Electronics for LHC Experiments

11. Channel Signal Rejection • Signal coupling between ADC adjacent channels was measured • FS 2.5MHz input signal on ADC2 • Worst case signal rejection measured on ADC2 –75dBFS 9th Workshop on Electronics for LHC Experiments

12. VCM IBIAS FE STG CLK VREF BE STG DIG CORR DCP DGI ChipMicrograph • Performance Summary • 12 bit Quad Pipeline ADC • 0.25um CMOS 1P3M 2.5V • ENOB=11bit @ 40Ms/s Fin=2.5MHz • SNR=68dB • SNDR=67dB • SFDR=70dB • DNL/INL< 0.7/ 1.5LSB • Area=3.96mm2/2ADC • Die size=11.8mm2 • DCP area 0.29mm2 (1.18nF) • 412mW power dissipation @ 2.5V(4ADCs + VCM & BIAS) • 144pin fpBGA Package • 150mW power dissipation per channel(gain amplif + dig. log.) 9th Workshop on Electronics for LHC Experiments

13. Monolithic ADCs 9th Workshop on Electronics for LHC Experiments

14. Cascode NMOS Cascode PMOS CMOS Switches Radiation Tolerant Layout Layout area overhead due to radiation tolerant structures • Layout area overhead • Switches: 23% • NMOS cascode compared to CMOS cascode shared drain: 25% • Drain region not shared • W>14um =>same area • W ~ 4um =>3X larger 9th Workshop on Electronics for LHC Experiments

15. Summary • A competitive ADC macro implementation was shown: Quad 12bit 40Ms/s low power • Test chip implemented proving design on spec for external references: ENOB=11bit @ 40Ms/s • Power consumption of 4 channels is less than 1 channel of previous implementation 9th Workshop on Electronics for LHC Experiments

16. Status & Planning • Prototype submitted for Fab in March 2003 • Manufacturing, packaging and system evaluation to end of September 2003 • Circuit revision and optimization on going • Engineering run submission mid October 2003 • 5000 production chips for final system assessment expected for early 2004 9th Workshop on Electronics for LHC Experiments