1 / 4

Readout Architecture for MuCh (conceptual)

Detector. FEB. Serial Hub. FEB. ROC. ROC. DCB. DPB. Readout Architecture for MuCh (conceptual). Cave. 60mt. Annex Bldg. Cu-500Mbps. Fibre- 2.5Gbps. Fibre. FEDC Crate.

red
Download Presentation

Readout Architecture for MuCh (conceptual)

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Detector FEB Serial Hub FEB ROC ROC DCB DPB Readout Architecture for MuCh (conceptual) Cave 60mt. Annex Bldg Cu-500Mbps Fibre- 2.5Gbps Fibre FEDC Crate • FEE ASIC interface is based on 500 Mbps LVDS links. A minimal  interface has 3 LVDS pairs, 1 clock, 1 uplink, 1 downlink. • A 'Hub' allows to aggregate several 500 Mbps links onto a smaller  number of 2.5 Gbps links FDC Crate - Feature Extraction and Data Combiner Crate ( may be good name can be given) - Several ROCs -Data Processing Board and Data Combining Board (DPB+DCB) CBM Collaboration Meeting, VECC, Kolkata

  2. Readout Architecture for MuCh (conceptual) How many channels in a FEE-ASIC ? - Is same TRD FEE-ASICcan be used? How many FEE-ASIC on a FEB ? How many FEBs can handle a Serial-ASIC ? How many Serial-ASICs can be put on a Serial Hub? How many channels of Serial Hub can handle one ROC? How many ROCs will be put on FDC crate? Some building blocks are available or are are clearly assigned as work packages to a group ( from Walter Muller’s mail): - the CBMnet protocol engine will be done in Mannheim (Bruening) - the 500 Mbps physical layer will be done in Mannheim (Bruening/Fischer)- the 2.5 Gbps SERDES will be done at IIT-KGP - a ROC prototyping platform will be done in Heidelberg (Kebschull) CBM Collaboration Meeting, VECC, Kolkata

  3. Readout Architecture for MuCh (conceptual) We have many things to do: connection FEB->'Hub': the current picture is to have FEB's with   a certain number of FEE-ASIC and the 'Hub' on a separate PCB, and   to connect them with some Cu-cables. - type of cabling - type of connectors - cable length etc. 'Hub': data aggregator - combining 'Hub' logic function and the 'OptoConverter' function - to connect  n 500 Mbps links to m 2.5 Gbps links.    - what 'n' and 'm' should be get useful building blocks for the system. 'Hub' logic: before we'll go for an ASIC we'll certainly test the    logic intensively in FPGA based implementations. There are many    aspects to consider, design, implement, and test. CBM Collaboration Meeting, VECC, Kolkata

  4. Readout Architecture for MuCh (conceptual) • What we are doing: • FEBs for MuCh • - fabricating ROCs with existing design • - 2.5 Gbps Serial ASIC for HUB • I think, • we should also take up the work for data processing and data combining ( DPB+DCB) • What are the features for MUCH to be extracted? • How to implement it ( Hardware or Software )? • Some WPs may be defined So far, we have mostly just read and gained some experiences about MuCh electronics. Now, time is approaching to deliver things in some concrete fashion. We should start Thinking in that direction and designate the manpower for different WPs. Many issues are common to both of MuCh and TRD. Muller is already in the process to form a work group having both TRD and MuCh members to work with some well defined WPs. This workgroups should meet once in a week through EVO to share their knowledge progress. CBM Collaboration Meeting, VECC, Kolkata

More Related