VLSI Arithmetic Lecture 5

VLSI ArithmeticLecture 5 Prof. Vojin G. Oklobdzija University of California http://www.ece.ucdavis.edu/acsel

Review Lecture 4

Ling’s Adder Huey Ling, “High-Speed Binary Adder” IBM Journal of Research and Development, Vol.5, No.3, 1981. Used in: IBM 3033, IBM S370/168, Amdahl V6, HP etc.

Ling’s Derivations ai bi ci+1 ci si define: gi implies Ci+1 which implies Hi+1 , thus: gi= gi Hi+1 Computer Arithmetic

Ling’s Derivations From: and because: fundamental expansion Now we need to derive Sum equation Computer Arithmetic

Ling Adder Ling’s equations: Variation of CLA: Ling, IBM J. Res. Dev, 5/81 Computer Arithmetic

Ling Adder ai-1 ai bi-1 bi ci+1 ci-1 ci si-1 si Hi+1 Hi gi, ti gi-1, ti-1 Ling’s equation: Variation of CLA: Ling uses different transfer function. Four of those functions have desired properties (Ling’s is one of them) see: Doran, IEEE Trans on Comp. Vol 37, No.9 Sept. 1988. Computer Arithmetic

Ling Adder Conventional: Fan-in of 5 Ling: Fan-in of 4 Computer Arithmetic

Advantages of Ling’s Adder • Uniform loading in fan-in and fan-out • H16 contains 8 terms as compared to G16 that contains 15. • H16 can be implemented with one level of logic (in ECL), while G16 can not (with 8-way wire-OR). (Ling’s adder takes full advantage of wired-OR, of special importance when ECL technology is used - his IBM limitation was fan-in of 4 and wire-OR of 8) Computer Arithmetic

Ling: Weinberger Notes Computer Arithmetic

Advantage of Ling’s Adder • 32-bit adder used in: IBM 3033, IBM S370/ Model168, Amdahl V6. • Implements 32-bit addition in 3 levels of logic • Implements 32-bit AGEN: B+Index+Disp in 4 levels of logic (rather than 6) • 5 levels of logic for 64-bit adder used in HP processor Computer Arithmetic

Implementation of Ling’s Adder in CMOS(S. Naffziger, “A Subnanosecond 64-b Adder”, ISSCC ‘ 96) Computer Arithmetic

S. Naffziger, ISSCC’96 Computer Arithmetic

Ling Adder Critical Path Computer Arithmetic

Ling Adder: Circuits Computer Arithmetic

LCS4 – Critical G Path Computer Arithmetic

LCS4 – Logical Effort Delay Computer Arithmetic

Results: • 0.5u Technology • Speed: 0.930 nS • Nominal process, 80C, V=3.3V See: S. Naffziger, “A Subnanosecond 64-b Adder”, ISSCC ‘ 96 Computer Arithmetic

Prefix Addersand Parallel Prefix Adders

from: Ercegovac-Lang Computer Arithmetic

Prefix Adders Following recurrence operation is defined: (g, p)o(g’,p’)=(g+pg’, pp’) such that: (g0, p0) i=0 Gi, Pi = (gi, pi)o(Gi-1, Pi-1 ) 1 ≤ i ≤ n ci+1 = Gi for i=0, 1, ….. n (g-1, p-1)=(cin,cin) c1 = g0+ p0 cin This operation is associative, but not commutative It can also span a range of bits (overlapping and adjacent) Computer Arithmetic

from: Ercegovac-Lang Computer Arithmetic

Parallel Prefix Adders: variety of possibilities from: Ercegovac-Lang Computer Arithmetic

Pyramid Adder:M. Lehman, “A Comparative Study of Propagation Speed-up Circuits in Binary Arithmetic Units”, IFIP Congress, Munich, Germany, 1962. Computer Arithmetic

Parallel Prefix Adders: variety of possibilities from: Ercegovac-Lang Computer Arithmetic

Hybrid BK-KS Adder Computer Arithmetic

Parallel Prefix Adders: S. Knowles 1999 operation is associative: h>i≥j≥k operation is idempotent: h>i≥j≥k produces carry: cin=0 Computer Arithmetic

Parallel Prefix Adders: Ladner-Fisher Exploits associativity, but not idempotency. Produces minimal logical depth Computer Arithmetic

Parallel Prefix Adders: Ladner-Fisher(16,8,4,2,1) Two wires at each level. Uniform, fan-in of two. Large fan-out (of 16; n/2); Large capacitive loading combined with the long wires (in the last stages) Computer Arithmetic

Parallel Prefix Adders: Kogge-Stone Exploits idempotency to limit the fan-out to 1. Dramatic increase in wires. The wire span remains the same as in Ladner-Fisher. Buffers needed in both cases: K-S, L-F Computer Arithmetic

Kogge-Stone Adder Computer Arithmetic

Parallel Prefix Adders: Brent-Kung • Set the fan-out to one • Avoids explosion of wires (as in K-S) • Makes no sense in CMOS: • fan-out = 1 limit is arbitrary and extreme • much of the capacitive load is due to wire (anyway) • It is more efficient to insert buffers in L-F than to use B-K scheme Computer Arithmetic

Brent-Kung Adder Computer Arithmetic

Parallel Prefix Adders: Han-Carlson • Is a hybrid synthesis of L-F and K-S • Trades increase in logic depth for a reduction in fan-out: • effectively a higher-radix variant of K-S. • others do it similarly by serializing the prefix computation at the higher fan-out nodes. • Others, similarly trade the logical depth for reduction of fan-out and wire. Computer Arithmetic

Parallel Prefix Adders: variety of possibilities from: Knowles bounded by L-F and K-S at ends Computer Arithmetic

Parallel Prefix Adders: variety of possibilitiesKnowles 1999 Following rules are used: • Lateral wires at the jth level span 2j bits • Lateral fan-out at jth level is power of 2 up to 2j • Lateral fan-out at the jth level cannot exceed that a the (j+1)th level. Computer Arithmetic

Parallel Prefix Adders: variety of possibilitiesKnowles 1999 • The number of minimal depth graphs of this type is given in: • at 4-bits there is only K-S and L-F, afterwards there are several new possibilities. Computer Arithmetic

VLSI Arithmetic Lecture 5