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This lecture discusses the implementation and delay calculation for a 32-bit Variable Block Adder, comparing it to other adder architectures. Various optimization techniques and logic implementations are explored.
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VLSI ArithmeticLecture 4 Prof. Vojin G. Oklobdzija University of California http://www.ece.ucdavis.edu/acsel
Review Lecture 3
Variable Block Adder(Oklobdzija, Barnes: IBM 1985) Computer Arithmetic
Carry-chain of a 32-bit Variable Block Adder(Oklobdzija, Barnes: IBM 1985) Computer Arithmetic
Carry-chain of a 32-bit Variable Block Adder(Oklobdzija, Barnes: IBM 1985) 6 5 5 4 4 3 3 D=9 1 1 Any-point-to-any-point delay = 9 D as compared to 12 D for CSKA Computer Arithmetic
Carry-chain block size determination for a 32-bit Variable Block Adder(Oklobdzija, Barnes: IBM 1985) Computer Arithmetic
Delay Calculation for Variable Block Adder(Oklobdzija, Barnes: IBM 1985) Delay model: Computer Arithmetic
Variable Block Adder(Oklobdzija, Barnes: IBM 1985) Variable Group Length Oklobdzija, Barnes, Arith’85 Computer Arithmetic
Carry-chain of a 32-bit Variable Block Adder(Oklobdzija, Barnes: IBM 1985) Variable Block Lengths • No closed form solution for delay • It is a dynamic programming problem Computer Arithmetic
Delay Comparison: Variable Block Adder(Oklobdzija, Barnes: IBM 1985) Computer Arithmetic
Delay Comparison: Variable Block Adder Square Root Dependency VBA Log Dependency CLA VBA- Multi-Level Computer Arithmetic
Circuit Issues • Adder speed can not be estimated based on: • logic gates in the critical path • number of transistors in the path • logic levels in the path • Estimating Adders speed is much more complex and many of the “fast” schemes may be misleading you. Computer Arithmetic
Fan-Out Dependency Computer Arithmetic
Fan-In Dependency This looks like “Logical Effort” (1985) Computer Arithmetic
Delay Comparison: Variable Block Adder(Oklobdzija, Barnes: IBM 1985) Computer Arithmetic
Carry-Lookahead Adder(Weinberger and Smith, 1958) ARITH-13: Presenting Achievement Award to Arnold Weinberger of IBM (who invented CLA adder in 1958) Ref: A. Weinberger and J. L. Smith, “A Logic for High-Speed Addition”, National Bureau of Standards, Circ. 591, p.3-12, 1958. Computer Arithmetic
CLA Definitions: One-bit adder Computer Arithmetic
CLA Definitions: 4-bit Adder Computer Arithmetic
Carry-Lookahead Adder: 4-bits Gj Pj Computer Arithmetic
Carry-Lookahead Adder One gate delay D to calculate p, g One D to calculate P and two for G Three gate delays To calculate C4(j+1) Compare that to 8 D in RCA ! Computer Arithmetic
Carry-Lookahead Adder(Weinberger and Smith) Additional two gate delays C16 will take a total of 5D vs. 32D for RCA ! Computer Arithmetic
32-bit Carry Lookahead Adder Computer Arithmetic
Carry-Lookahead Adder(Weinberger and Smith: original derivation, 1958 ) Computer Arithmetic
Carry-Lookahead Adder(Weinberger and Smith: original derivation ) Computer Arithmetic
Carry-Lookahead Adder (Weinberger and Smith)please notice the similarity with Parallel-Prefix Adders ! Computer Arithmetic
Carry-Lookahead Adder (Weinberger and Smith)please notice the similarity with Parallel-Prefix Adders ! Computer Arithmetic
Motorola: CLA Implementation Example A. Naini, D. Bearden and W. Anderson, “A 4.5nS 96b CMOS Adder Design”, Proceedings of the IEEE Custom Integrated Circuits Conference, May 3-6, 1992.
Critical path in Motorola's 64-bit CLA 4.8nS 1.05nS 1.7nS 3.75nS 2.7nS 2.0nS 2.35nS Computer Arithmetic
Motorola's 64-bit CLAconventional PG Block no better situation here ! carry ripples locally 5-transistors in the path Basically, this is MCC performance with Carry-Skip. One should not expect any better results than VBA. Computer Arithmetic
Motorola's 64-bit CLAModified PG Block Intermediate propagate signals Pi:0 are generated to speed-up C3 still critical path resembles MCC Computer Arithmetic
Motorola's 64-bit CLA 3.9nS 1.8nS 2.2nS 3.55nS 2.9nS 3.2nS Computer Arithmetic
3.9nS 4.8nS 1.8nS 1.05nS 2.2nS 1.7nS 3.55nS 3.75nS 2.9nS 3.2nS 2.7nS 2.0nS 2.35nS Computer Arithmetic
Delay Optimized CLA B. Lee, V. G. Oklobdzija Journal of VLSI Signal Processing, Vol.3, No.4, October 1991
Delay Optimized CLA: Lee-Oklobdzija ‘91 (a.) Fixed groups and levels (b.) variable-sized groups, fixed levels (c.) variable-sized groups and fixed levels (d.) variable-sized groups and levels Computer Arithmetic
Two-Levels of Logic Implementation of the Carry Block Computer Arithmetic
Two-Levels of Logic Implementation of the Carry-Lookahead Block Computer Arithmetic
Three-Levels of Logic Implementation of the Carry Block (restricted fan-in) Computer Arithmetic
Three-Levels of Logic Implementation of the Carry Lookahead (restricted fan-in) Computer Arithmetic
Delay Optimized CLA: Lee-Oklobdzija ‘91 Delay: Three-level BCLA Delay: Two-level BCLA Computer Arithmetic
Delay Optimized CLA: Lee-Oklobdzija ‘91 (a.) 2-level BCLA D=8.5nS (b.) 3-level BCLA D=8.9nS Computer Arithmetic
Ling’s Adder Huey Ling, “High-Speed Binary Adder” IBM Journal of Research and Development, Vol.5, No.3, 1981. Used in: IBM 3033, IBM 168, Amdahl V6, HP etc.
Ling’s Derivations ai bi ci+1 ci si define: gi implies Ci+1 which implies Hi+1 , thus: gi= gi Hi+1 Computer Arithmetic
Ling’s Derivations From: and because: fundamental expansion Now we need to derive Sum equation Computer Arithmetic
Ling Adder Ling’s equations: Variation of CLA: Ling, IBM J. Res. Dev, 5/81 Computer Arithmetic
Ling Adder Ling’s equation: Variation of CLA: Ling uses different transfer function. Four of those functions have desired properties (Ling’s is one of them) see: Doran, IEEE Trans on Comp. Vol 37, No.9 Sept. 1988. Computer Arithmetic
Ling Adder Conventional: Fan-in of 5 Ling: Fan-in of 4 Computer Arithmetic
Advantages of Ling’s Adder • Uniform loading in fan-in and fan-out • H16 contains 8 terms as compared to G16 that contains 15. • H16 can be implemented with one level of logic (in ECL), while G16 can not. (Ling’s adder takes full advantage of wired-OR, of special importance when ECL technology is used) Computer Arithmetic